Invention Application
- Patent Title: INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION THEREOF
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Application No.: US16048957Application Date: 2018-07-30
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Publication No.: US20190067197A1Publication Date: 2019-02-28
- Inventor: Chia-Ta YU , Kai-Hsuan LEE , Yen-Ming CHEN , Chi On CHUI , Sai-Hooi YEONG
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/532 ; C23C14/02 ; H01L21/768 ; H01L21/288 ; H01L21/02 ; C23C16/34 ; C23C16/04 ; C23C16/02 ; C23C14/06 ; C23C14/04 ; H01L23/522

Abstract:
Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.
Public/Granted literature
- US10777504B2 Interconnect structure for semiconductor device and methods of fabrication thereof Public/Granted day:2020-09-15
Information query
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