公开(公告)号：US20190067197A1

公开(公告)日：2019-02-28

申请号：US16048957

申请日：2018-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta YU ,  Kai-Hsuan LEE ,  Yen-Ming CHEN ,  Chi On CHUI ,  Sai-Hooi YEONG

IPC: H01L23/528 ,  H01L23/532 ,  C23C14/02 ,  H01L21/768 ,  H01L21/288 ,  H01L21/02 ,  C23C16/34 ,  C23C16/04 ,  C23C16/02 ,  C23C14/06 ,  C23C14/04 ,  H01L23/522

Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

公开(公告)号：US20180083109A1

公开(公告)日：2018-03-22

申请号：US15814129

申请日：2017-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta YU ,  Sheng-Chen WANG ,  Wei-Yuan LU ,  Chien-I KUO ,  Li-Li SU ,  Feng-Cheng YANG ,  Yen-Ming CHEN ,  Sai-Hooi YEONG

IPC: H01L29/24 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/08 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2224/056

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).

公开(公告)号：US20240145546A1

公开(公告)日：2024-05-02

申请号：US18405957

申请日：2024-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta YU ,  Yen-Chieh HUANG ,  Yi-Hsien TU ,  I-Hsieh WONG

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/761 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/02378 ,  H01L21/761 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/167 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/02579 ,  H01L29/42392

Abstract: The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers. The method further includes removing the sacrificial gate structure, removing the first nano-sheet layers, and forming a gate structure around the second nano-sheet layers.

公开(公告)号：US20200161240A1

公开(公告)日：2020-05-21

申请号：US16722630

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta YU ,  Kai-Hsuan LEE ,  Yen-Ming CHEN ,  Chi On CHUI ,  Sai-Hooi YEONG

IPC: H01L23/528 ,  H01L21/3105 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  C23C16/34 ,  C23C16/04 ,  C23C16/02 ,  C23C14/06 ,  C23C14/04 ,  C23C14/02

Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

公开(公告)号：US20220384576A1

公开(公告)日：2022-12-01

申请号：US17333276

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ta YU ,  Yen-Chieh Huang ,  Yi-Hsien Tu ,  I-Hsieh Wong

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/167 ,  H01L21/761 ,  H01L27/092

Abstract: The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers. The method further includes removing the sacrificial gate structure, removing the first nano-sheet layers, and forming a gate structure around the second nano-sheet layers.

公开(公告)号：US20190131423A1

公开(公告)日：2019-05-02

申请号：US15799385

申请日：2017-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-An LIN ,  Chun-Hsiung LIN ,  Chia-Ta YU ,  Sai-Hooi YEONG ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, a bottom semiconductor fin, at least one sidewall structure, a top semiconductor fin, and a gate structure. The bottom semiconductor fin is disposed on the substrate. The sidewall structure protrudes from the semiconductor fin. The top semiconductor fin is disposed on the bottom semiconductor fin. The top semiconductor fin includes a channel portion and at least one source/drain portion. The source/drain portion is disposed between the channel portion and the sidewall structure. The gate structure covers the channel portion of the top semiconductor fin.

公开(公告)号：US20190067194A1

公开(公告)日：2019-02-28

申请号：US15692439

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta YU ,  Kai-Hsuan LEE ,  Yen-Ming CHEN ,  Chi On CHUI ,  Sai-Hooi YEONG

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

公开(公告)号：US20170125304A1

公开(公告)日：2017-05-04

申请号：US15242155

申请日：2016-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Chen WANG ,  Kai-Hsuan LEE ,  Sai-Hooi YEONG ,  Chia-Ta YU

IPC: H01L21/8238 ,  H01L29/10 ,  H01L27/092 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/823821 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: In manufacturing a semiconductor device, a stack of first and second semiconductor layers are formed. A fin structure is formed by patterning the first and second semiconductor layers. A cover layer is formed on a bottom part of the fin structure so as to cover side walls of the bottom portion of the fin structure and a bottom part of side walls of the upper portion of the fin structure. An insulating layer is formed so that the fin structure is embedded in the insulating layer. A part of the upper portion is removed so that an opening is formed in the insulating layer. A third semiconductor layer is formed in the opening on the remaining layer of the second semiconductor layer. The insulating layer is recessed so that a part of the third semiconductor layer is exposed from the insulating layer, and a gate structure is formed.