- 专利标题: MEMORY CIRCUIT HAVING SHARED WORD LINE
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申请号: US16207030申请日: 2018-11-30
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公开(公告)号: US20190103158A1公开(公告)日: 2019-04-04
- 发明人: Hidehiro FUJIWARA , Li-Wen WANG , Yen-Huei CHEN , Hung-Jen LIAO
- 申请人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 主分类号: G11C11/419
- IPC分类号: G11C11/419 ; H01L27/11 ; H01L27/02 ; G11C11/418 ; G11C8/14
摘要:
A circuit includes a column of memory cells, a first read data line coupled exclusively with a first subset of memory cells of the column of memory cells, a second read data line coupled exclusively with a second subset of memory cells of the column of memory cells, and a plurality of read word lines. Each read word line of the plurality of read word lines is coupled with a memory cell of the first subset of memory cells and with a memory cell of the second subset of memory cells.
公开/授权文献
- US10783955B2 Memory circuit having shared word line 公开/授权日:2020-09-22