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    SEMICONDUCTOR DEVICE INCLUDING DISTRIBUTED WRITE DRIVING ARRANGEMENT
    2.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DISTRIBUTED WRITE DRIVING ARRANGEMENT 有权

    公开(公告)号：US20220366965A1

    公开(公告)日：2022-11-17

    申请号：US17816048

    申请日：2022-07-29

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Li-Wen WANG ,  Jonathan Tsung-Yung CHANG ,  Yen-Huei CHEN

    IPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C11/4096 ,  G11C5/06 ,  G11C11/419 ,  H01L21/48 ,  H01L27/11

    摘要： A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells that are connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver and local write drivers included correspondingly in the segments; and the global write driver including a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line, and the global write driver and the local write drivers each including first inversion couplings (coupled in parallel between the GWB line and the LWB line) and second inversion couplings (coupled in parallel between the GWB_bar line and the LWB_bar line).

    MEMORY COMPUTATION CIRCUIT
    3.
    发明申请
    MEMORY COMPUTATION CIRCUIT 有权

    公开(公告)号：US20220328096A1

    公开(公告)日：2022-10-13

    申请号：US17808536

    申请日：2022-06-23

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yen-Huei CHEN ,  Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG

    IPC分类号： G11C11/419 ,  G11C11/412 ,  G06N3/08 ,  G06F17/16

    摘要： A memory circuit includes a first memory array including first memory cells wherein a plurality of first word lines is coupled with a plurality of rows of first memory cells in a first segment of the first memory array, and a plurality of second word lines is coupled with the plurality of rows of first memory cells in a second segment of the first memory array. The memory circuit also includes a read circuit configured to retrieve data from the first memory cells of the first memory array and a computation circuit configured to perform a matrix computation by combining first data retrieved from the first memory cells of the first segment with second data retrieved from the first memory cells of the second segment.

    MEMORY CIRCUIT HAVING SHARED WORD LINE
    6.
    发明申请
    MEMORY CIRCUIT HAVING SHARED WORD LINE 审中-公开
    具有共享字线的存储器电路

    公开(公告)号：US20160372181A1

    公开(公告)日：2016-12-22

    申请号：US15251260

    申请日：2016-08-30

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hidehiro FUJIWARA ,  Li-Wen WANG ,  Yen-Huei CHEN ,  Hung-Jen LIAO

    IPC分类号： G11C11/419

    CPC分类号： G11C11/419 ,  G11C8/14 ,  G11C11/418 ,  H01L27/0207 ,  H01L27/1116

    摘要： A memory circuit includes first and second memory cells. The first memory cell has an access port having a pass gate. The second memory cell also has an access port having a pass gate. The first and second memory cells abut one another along a column direction. The circuit includes at least one conductive structure over the first and second memory cells. The conductive structure may be two interconnected conductive lines. The conductive structure extends along a row direction in a conductive layer and is electrically coupled to the gate terminals of the pass gates.

    摘要翻译： 存储电路包括第一和第二存储单元。 第一存储器单元具有具有通孔的访问端口。 第二存储单元还具有具有通孔的访问端口。 第一和第二存储器单元沿列方向彼此邻接。 电路包括在第一和第二存储器单元上的至少一个导电结构。 导电结构可以是两个互连的导电线。 导电结构在导电层中沿着行方向延伸并且电耦合到通孔的栅极端子。

    STATIC RANDOM ACCESS MEMORY AND METHOD OF OPERATING THE SAME
    7.
    发明申请
    STATIC RANDOM ACCESS MEMORY AND METHOD OF OPERATING THE SAME 有权
    静态随机访问存储器及其操作方法

    公开(公告)号：US20160293248A1

    公开(公告)日：2016-10-06

    申请号：US14696795

    申请日：2015-04-27

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Wei-Cheng WU ,  Kao-Cheng LIN ,  Wei Min CHAN ,  Yen-Huei CHEN

    IPC分类号： G11C11/419

    CPC分类号： G11C11/419

    摘要： A static random access memory (SRAM) including at least a memory cell array, a first data line, a second data line, a third data line and a driver circuit. The first data line is electrically coupled with the memory cell array. The second data line is electrically coupled with the memory cell array. The driver circuit is electrically coupled with the first data line, the second data line and the third data line. The driver circuit includes a recovery circuit electrically coupled with the first data line, the second data line and the third data line. During a write operation of the SRAM, the recovery circuit is configured to pull a voltage level of the first data line to a first voltage level when the recovery circuit is enabled.

    摘要翻译： 包括至少存储单元阵列，第一数据线，第二数据线，第三数据线和驱动器电路的静态随机存取存储器（SRAM）。 第一数据线与存储单元阵列电耦合。 第二数据线与存储单元阵列电耦合。 驱动电路与第一数据线，第二数据线和第三数据线电耦合。 驱动器电路包括与第一数据线，第二数据线和第三数据线电耦合的恢复电路。 在SRAM的写入操作期间，恢复电路被配置为当恢复电路被使能时将第一数据线的电压电平拉到第一电压电平。

    STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME
    8.
    发明申请
    STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME 有权

    公开(公告)号：US20220093172A1

    公开(公告)日：2022-03-24

    申请号：US17541240

    申请日：2021-12-02

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chih-Yu LIN ,  Wei-Cheng WU ,  Kao-Cheng LIN ,  Yen-Huei CHEN

    IPC分类号： G11C11/419

    摘要： A static random access memory (SRAM) includes a first memory cell array, a second memory cell array, a first data line coupled to the first memory cell array and the second memory cell array, a second data line coupled to the first memory cell array and the second memory cell array, a primary driver circuit coupled to at least the first data line, and a supplementary driver circuit coupled to at least the first data line. The supplementary driver circuit is configured to receive a supplementary driver circuit enable signal, sense a voltage of a first signal of the first data line, and pull the voltage of the first signal to a first voltage level during a write operation of a first memory cell in the first memory cell array in response to at least a first NOR output signal.

    FOUR CPP WIDE MEMORY CELL WITH BURIED POWER GRID, AND METHOD OF FABRICATING SAME
    9.
    发明申请
    FOUR CPP WIDE MEMORY CELL WITH BURIED POWER GRID, AND METHOD OF FABRICATING SAME 有权

    公开(公告)号：US20210408011A1

    公开(公告)日：2021-12-30

    申请号：US17225627

    申请日：2021-04-08

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hidehiro FUJIWARA ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Wei-Chang ZHAO ,  Yi-Hsin NIEN

    IPC分类号： H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  G06F30/392

    摘要： A memory device including: active regions; gate electrodes which are substantially aligned relative to four corresponding track lines such that the memory device has a width of four contacted poly pitch (4 CPP) and are electrically coupled to the active regions; contact-to-transistor-component structures (MD structures) which are electrically coupled to the active regions, and are interspersed among corresponding ones of the gate electrodes; via-to-gate/MD (VGD) structures which are electrically coupled to the gate electrodes and the MD structures; conductive segments which are in a first layer of metallization (M_1st layer), and are electrically coupled to the VGD structures; buried contact-to-transistor-component structures (BVD structures) which are electrically coupled to the active regions; and buried conductive segments which are in a first buried layer of metallization (BM_1st layer), and are electrically coupled to the BVD structures, and correspondingly provide a first reference voltage or a second reference voltage.