- 专利标题: Prevention of Contact Bottom Void in Semiconductor Fabrication
-
申请号: US16242720申请日: 2019-01-08
-
公开(公告)号: US20190164842A1公开(公告)日: 2019-05-30
- 发明人: Yun Lee , Chung-Ting Ko , Chen-Ming Lee , Mei-Yun Wang , Fu-Kai Yang
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 主分类号: H01L21/8234
- IPC分类号: H01L21/8234 ; H01L27/088
摘要:
A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.
公开/授权文献
信息查询
IPC分类: