发明申请
- 专利标题: WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURE
-
申请号: US16293201申请日: 2019-03-05
-
公开(公告)号: US20190198376A1公开(公告)日: 2019-06-27
- 发明人: Darrell D. TRUHITTE , James P. LETTERMAN, JR.
- 申请人: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- 申请人地址: US AZ Phoenix
- 专利权人: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- 当前专利权人: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- 当前专利权人地址: US AZ Phoenix
- 主分类号: H01L21/683
- IPC分类号: H01L21/683 ; H01L23/00 ; H01L23/31 ; H01L21/48 ; H01L21/56
摘要:
Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
公开/授权文献
信息查询
IPC分类: