- 专利标题: TRANSISTOR STRUCTURE AND SEMICONDUCTOR LAYOUT STRUCTURE
-
申请号: US15879929申请日: 2018-01-25
-
公开(公告)号: US20190198502A1公开(公告)日: 2019-06-27
- 发明人: CHING-CHIA HUANG , TSENG-FU LU , WEI-MING LIAO
- 申请人: NANYA TECHNOLOGY CORPORATION
- 主分类号: H01L27/108
- IPC分类号: H01L27/108 ; H01L29/423 ; H01L29/06 ; H01L29/78
摘要:
The present disclosure provides a transistor structure and a semiconductor layout structure. The transistor structure includes an active region, a buried gate structure disposed in the active region, a plurality of first dielectric layers disposed over sidewalls of the buried gate structure, and a source/drain region disposed in the active region at two opposite sides of the buried gate structure. In some embodiments, the buried gate structure includes a first portion and a second portion perpendicular to the first portion. In some embodiments, the buried gate structure is separated from the source/drain region by the first dielectric layers as viewed in a top view.
公开/授权文献
- US10381351B2 Transistor structure and semiconductor layout structure 公开/授权日:2019-08-13