公开(公告)号：US20220085180A1

公开(公告)日：2022-03-17

申请号：US17534799

申请日：2021-11-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHING-CHIA HUANG ,  TSENG-FU LU

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L27/108 ,  H01L27/088

摘要： The present disclosure provides a method for preparing a semiconductor device with a T-shaped buried gate electrode. The method includes forming an isolation structure in a semiconductor substrate to define an active region, and forming a doped region in the active region. The method also includes etching the semiconductor substrate to form a first trench and a second trench. The first trench has a first portion extending across the doped region and a second portion extending away from the first portion, and the second trench has a third portion extending across the doped region and a fourth portion extending away from the third portion. The method further includes forming a first gate electrode in the first trench and a second gate electrode in the second trench.

公开(公告)号：US20190198676A1

公开(公告)日：2019-06-27

申请号：US15894580

申请日：2018-02-12

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHENG-HSIEN HSIEH ,  TSENG-FU LU ,  JHEN-YU TSAI ,  CHING-CHIA HUANG ,  WEI-MING LIAO

IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L29/66

摘要： The present disclosure provides a semiconductor structure including a substrate, a bottom gate portion disposed in the substrate, a top gate portion stacked over the bottom gate portion, a first channel layer sandwiched between the top gate portion and the bottom gate portion, and a source/drain region disposed in the substrate at two opposite sides of the top gate portion.

公开(公告)号：US20210408251A1

公开(公告)日：2021-12-30

申请号：US16916696

申请日：2020-06-30

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHING-CHIA HUANG ,  TSENG-FU LU

IPC分类号： H01L29/423 ,  H01L27/088 ,  H01L21/8234

摘要： The present disclosure provides a semiconductor device with a T-shaped buried gate electrode and a method for forming the semiconductor device. The semiconductor device includes a semiconductor substrate having an active region, and a first gate electrode disposed in the semiconductor substrate. The semiconductor device also includes a first source/drain region and a second source/drain region disposed in the active region and at opposite sides of the first gate electrode. The first gate electrode has a first portion extending across the active region and a second portion extending into the first source/drain region.

公开(公告)号：US20190198502A1

公开(公告)日：2019-06-27

申请号：US15879929

申请日：2018-01-25

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHING-CHIA HUANG ,  TSENG-FU LU ,  WEI-MING LIAO

IPC分类号： H01L27/108 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L27/10823 ,  H01L27/10891 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7827 ,  H01L29/7831

摘要： The present disclosure provides a transistor structure and a semiconductor layout structure. The transistor structure includes an active region, a buried gate structure disposed in the active region, a plurality of first dielectric layers disposed over sidewalls of the buried gate structure, and a source/drain region disposed in the active region at two opposite sides of the buried gate structure. In some embodiments, the buried gate structure includes a first portion and a second portion perpendicular to the first portion. In some embodiments, the buried gate structure is separated from the source/drain region by the first dielectric layers as viewed in a top view.