- 专利标题: Trace Design for Bump-on-Trace (BOT) Assembly
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申请号: US16390953申请日: 2019-04-22
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公开(公告)号: US20190252347A1公开(公告)日: 2019-08-15
- 发明人: Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 主分类号: H01L23/00
- IPC分类号: H01L23/00 ; H01L23/498 ; H05K3/34
摘要:
A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small.
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