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    EMBEDDED SOI STRUCTURE FOR LOW LEAKAGE MOS CAPACITOR
    2.
    发明公开
    EMBEDDED SOI STRUCTURE FOR LOW LEAKAGE MOS CAPACITOR 审中-公开

    公开(公告)号：US20240071812A1

    公开(公告)日：2024-02-29

    申请号：US17823508

    申请日：2022-08-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chung-Lei Chen ,  Anhao Cheng ,  Meng-I Kang ,  Yen-Liang Lin

    IPC分类号： H01L21/762 ,  H01L21/84

    CPC分类号： H01L21/76275 ,  H01L21/76283 ,  H01L21/84

    摘要： A method for forming a semiconductor device includes providing a semiconductor substrate, implanting n-type impurities into a device region in the semiconductor substrate to form an implanted region and an un-implanted region. The method also includes forming an epitaxial layer on the semiconductor substrate and forming a trench surrounding the device region in direct contact with the implanted region. The method further includes performing a selective lateral etch through the trench to remove the implanted region to form a cavity under the epitaxial layer. The un-implanted region is retained to form a pillar under the epitaxial layer. Next, an insulating material is disposed in the cavity and the trench. The method forms a single crystalline region that is separated from the semiconductor substrate by the insulating material except at the pillar.

    Integrated Circuit Package and Method
    8.
    发明申请
    Integrated Circuit Package and Method 有权

    公开(公告)号：US20210193582A1

    公开(公告)日：2021-06-24

    申请号：US16868111

    申请日：2020-05-06

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chen-Hua Yu ,  Jen-Fu Liu ,  Ming Hung Tseng ,  Tsung-Hsien Chiang ,  Yen-Liang Lin ,  Tzu-Sung Huang

    IPC分类号： H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

    摘要： In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.

    Semiconductor packages and methods of forming the same
    9.
    发明授权
    Semiconductor packages and methods of forming the same 有权

    公开(公告)号：US10971477B2

    公开(公告)日：2021-04-06

    申请号：US16390275

    申请日：2019-04-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chen-Hua Yu ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Tzu-Sung Huang ,  Tin-Hao Kuo ,  Hao-Yi Tsai

    IPC分类号： H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L25/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

    摘要： A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis of the second via.