Invention Application
- Patent Title: METAL INTERCONNECT FUSE MEMORY ARRAYS
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Application No.: US15942952Application Date: 2018-04-02
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Publication No.: US20190304893A1Publication Date: 2019-10-03
- Inventor: Vincent DORGAN , Jeffrey HICKS , Uddalak BHATTACHARYA , Zhanping CHEN , Walid M. HAFEZ
- Applicant: Intel Corporation
- Main IPC: H01L23/50
- IPC: H01L23/50 ; H01L21/77 ; H01L21/768

Abstract:
Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.
Public/Granted literature
- US11239149B2 Metal interconnect fuse memory arrays Public/Granted day:2022-02-01
Information query
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