公开(公告)号：US20190304893A1

公开(公告)日：2019-10-03

申请号：US15942952

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Vincent DORGAN ,  Jeffrey HICKS ,  Uddalak BHATTACHARYA ,  Zhanping CHEN ,  Walid M. HAFEZ

IPC: H01L23/50 ,  H01L21/77 ,  H01L21/768

Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.

公开(公告)号：US20180145083A1

公开(公告)日：2018-05-24

申请号：US15575792

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Xiaoghong TONG ,  Walid M. HAFEZ ,  Zhiyong MA ,  Peng BAI ,  Chia-Hong JAN ,  Zhanping CHEN

IPC: H01L27/112 ,  G11C17/16 ,  H01L23/525

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L23/5252

Abstract: The controlled modification of an antifuse programming voltage is described. In one example, an antifuse circuit is formed on a substrate, including a gate area of the antifuse circuit. A molecule is implanted into the gate area to damage the structure of the gate area. Electrodes are formed over the gate areas to connect the antifuse circuit to other components.