公开(公告)号：US20190304893A1

公开(公告)日：2019-10-03

申请号：US15942952

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Vincent DORGAN ,  Jeffrey HICKS ,  Uddalak BHATTACHARYA ,  Zhanping CHEN ,  Walid M. HAFEZ

IPC: H01L23/50 ,  H01L21/77 ,  H01L21/768

Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.

公开(公告)号：US20190304906A1

公开(公告)日：2019-10-03

申请号：US15943009

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Vincent DORGAN ,  Jeffrey HICKS ,  Inanc MERIC

IPC: H01L23/525 ,  H01L29/78 ,  H01L23/64 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/105 ,  G11C11/40

Abstract: Embodiments herein may describe techniques for an integrated circuit including a FinFET transistor to be used as an antifuse element having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed. A FinFET transistor may include a source electrode in contact with a source area, a drain electrode in contact with a drain area, a fin area including silicon and between the source area and the drain area, and a gate electrode above the fin area and above the substrate. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20190304894A1

公开(公告)日：2019-10-03

申请号：US15942999

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Vincent DORGAN ,  Jeffrey HICKS ,  Miriam RESHOTKO ,  Abhishek SHARMA ,  Ilan TSAMERET

IPC: H01L23/50 ,  H01L23/48 ,  H01L29/51 ,  H01L23/498 ,  H01L21/82 ,  H01L23/522 ,  H01L23/525 ,  G11C17/16

Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate, an interlayer dielectric (ILD) layer above the metal interconnect with an opening to expose the metal interconnect at a bottom of the opening. A dielectric layer may conformally cover sidewalls and the bottom of the opening and in contact with the metal interconnect. An electrode may be formed within the opening, above the metal interconnect, and separated from the metal interconnect by the dielectric layer. After a programming voltage may be applied between the metal interconnect and the electrode to generate a current between the metal interconnect and the electrode, a conductive path may be formed through the dielectric layer to couple the metal interconnect and the electrode, changing the resistance between the metal interconnect and the electrode. Other embodiments may be described and/or claimed.