Invention Application
- Patent Title: METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING A MULTI-THICKNESS GATE TRENCH DIELECTRIC LAYER
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Application No.: US16443880Application Date: 2019-06-18
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Publication No.: US20190312036A1Publication Date: 2019-10-10
- Inventor: Tsuo-Wen Lu , Ger-Pin Lin , Tien-Chen Chan , Shu-Yen Chan
- Applicant: UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
- Priority: CN201710637712.8 20170731
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L21/28 ; H01L29/51 ; H01L21/02 ; H01L29/423 ; H01L29/66

Abstract:
A semiconductor device includes a semiconductor substrate having a gate trench including of an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.
Information query
IPC分类: