Invention Application
- Patent Title: STACKED III-V SEMICONDUCTOR COMPONENT
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Application No.: US16379008Application Date: 2019-04-09
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Publication No.: US20190312151A1Publication Date: 2019-10-10
- Inventor: Volker DUDEK
- Applicant: 3-5 Power Electronics GmbH
- Applicant Address: DE Dresden
- Assignee: 3-5 Power Electronics GmbH
- Current Assignee: 3-5 Power Electronics GmbH
- Current Assignee Address: DE Dresden
- Priority: DE102018002895.0 20180409
- Main IPC: H01L29/861
- IPC: H01L29/861 ; H01L29/06 ; H01L29/20 ; H01L29/32 ; H01L29/36

Abstract:
A stacked III-V semiconductor component having a stack with a top, a bottom, a side surface, and a longitudinal axis. The stack has a p+ region, an n− layer, and an n+ region. The p+ region, the n− layer, and the n+ region follow one another in the specified order along the longitudinal axis and are monolithic in design, and include a GaAs compound. The n+ region or the p+ region is a substrate layer. The stack has, in the region of the side surface, a first and a second peripheral, shoulder-like edge. The first edge is composed of the substrate layer; the second edge is composed of the n− layer or of an intermediate layer adjacent to the n− layer and to the p+ region and the first and the second peripheral edges each have a width of at least 10 μm.
Public/Granted literature
- US10784381B2 Stacked III-V semiconductor component Public/Granted day:2020-09-22
Information query
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