公开(公告)号：US11784261B2

公开(公告)日：2023-10-10

申请号：US17667105

申请日：2022-02-08

Applicant: 3-5 Power Electronics GmbH ,  AZUR SPACE Solar Power GmbH

Inventor： Volker Dudek ,  Jens Kowalsky ,  Riteshkumar Bhojani ,  Daniel Fuhrmann ,  Thorsten Wierzkowski

IPC: H01L29/868 ,  H01L29/207

CPC classification number: H01L29/868 ,  H01L29/207

Abstract: A stacked III-V semiconductor diode comprising or consisting of GaAs, with a heavily n-doped cathode layer, a heavily p-doped anode layer, and a drift region arranged between the cathode layer and the anode layer with a dopant concentration of at most 8·1015 cm−3, and a layer thickness of at least 10 μm, wherein the cathode layer has a delta layer section with a layer thickness of 0.1 μm to 2 μm and a dopant concentration of at least 1·1019 cm−3.

公开(公告)号：US20190312151A1

公开(公告)日：2019-10-10

申请号：US16379008

申请日：2019-04-09

Applicant: 3-5 Power Electronics GmbH

Inventor： Volker DUDEK

IPC: H01L29/861 ,  H01L29/06 ,  H01L29/20 ,  H01L29/32 ,  H01L29/36

Abstract: A stacked III-V semiconductor component having a stack with a top, a bottom, a side surface, and a longitudinal axis. The stack has a p+ region, an n− layer, and an n+ region. The p+ region, the n− layer, and the n+ region follow one another in the specified order along the longitudinal axis and are monolithic in design, and include a GaAs compound. The n+ region or the p+ region is a substrate layer. The stack has, in the region of the side surface, a first and a second peripheral, shoulder-like edge. The first edge is composed of the substrate layer; the second edge is composed of the n− layer or of an intermediate layer adjacent to the n− layer and to the p+ region and the first and the second peripheral edges each have a width of at least 10 μm.

公开(公告)号：US10312381B2

公开(公告)日：2019-06-04

申请号：US15936330

申请日：2018-03-26

Applicant: 3-5 Power Electronics GmbH

Inventor： Volker Dudek

IPC: H01L29/872 ,  H01L29/32 ,  H01L29/861 ,  H01L29/20 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/18 ,  H01L21/265 ,  H01L21/306

Abstract: A stacked III-V semiconductor diode that has an n+ layer having a dopant concentration of at least 1019 N/cm3, an n− layer having a dopant concentration of 1012 N/cm3 to 1016 N/cm3, a layer thickness of 10 μm to 300 μm, a p+ layer having a dopant concentration of 5·1018 N/cm3 to 5·1020 cm3 and a layer thickness greater than 2 μm, the layers following each other in the specified order, each including a GaAs compound or being made from a GaAs compound and having a monolithic design, the n+ layer or the p+ layer being a substrate, and a lower side of the n− layer being integrally connected to an upper side of the n+ layer. The stacked III-V semiconductor diode including a first defect layer having a layer thickness greater than 0.5 μm, the defect layer being situated within the n− layer.

公开(公告)号：US20180138320A1

公开(公告)日：2018-05-17

申请号：US15812432

申请日：2017-11-14

Applicant: 3-5 Power Electronics GmbH

Inventor： Volker DUDEK

IPC: H01L29/872 ,  H01L29/207 ,  H01L29/36 ,  H01L29/06 ,  H01L21/18

CPC classification number: H01L29/872 ,  H01L21/185 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/207 ,  H01L29/36 ,  H01L29/66204 ,  H01L29/861

Abstract: A stacked III-V semiconductor diode having an n+ substrate with a dopant concentration of at least 1019 cm−3 and a layer thickness of 50-400 μm, an n− layer with a dopant concentration of 1012-1016 cm−3 and a layer thickness of 10-300 μm, a p+ layer with a dopant concentration of 5·1018-5·1020 cm−3, including a GaAs compound and with a layer thickness greater than 2 μm, wherein the n+ substrate and the n− layer are integrally joined to one another. A doped intermediate layer with a layer thickness of 1-50 μm and a dopant concentration of 1012-1017 cm−3 is arranged between the n− layer and the p+ layer, and the intermediate layer is integrally joined to the n− layer and to the p+ layer.

公开(公告)号：US11699722B2

公开(公告)日：2023-07-11

申请号：US17579122

申请日：2022-01-19

Applicant: AZUR SPACE Solar Power GmbH ,  3-5 Power Electronics GmbH

Inventor： Daniel Fuhrmann ,  Gregor Keller ,  Clemens Waechter ,  Volker Dudek

IPC: H01L29/15 ,  H01L29/06 ,  H01L29/10 ,  H01L29/201 ,  H01L29/861

CPC classification number: H01L29/157 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/201 ,  H01L29/861

Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

公开(公告)号：US20220336315A1

公开(公告)日：2022-10-20

申请号：US17721000

申请日：2022-04-14

Applicant: 3-5 Power Electronics GmbH

Inventor： Jens KOWALSKY

IPC: H01L23/367 ,  H01L23/46 ,  H01L23/31 ,  H01L23/49

Abstract: Packaged semiconductor device having a heat sink, wherein the heat sink has a top, a bottom, lateral surfaces that connect the top to the bottom, and, extending within the heat sink, a cooling structure with an inlet line as well as an outlet line for a cooling medium, and is composed of an electrically conductive material with a first coefficient of thermal expansion at the top and with a second coefficient of thermal expansion at the bottom, a die is arranged on each of the top and the bottom of the heat sink and is connected to the heat sink in an electrically conductive manner, the coefficients of thermal expansion of the top and of the bottom of the heat sink correspond in each case to the coefficient of thermal expansion of the die arranged thereon or differ from the coefficient of thermal expansion of the die arranged thereon by at most 10% or by at most 20%.

公开(公告)号：US20220254938A1

公开(公告)日：2022-08-11

申请号：US17667274

申请日：2022-02-08

Applicant: 3-5 Power Electronics GmbH

Inventor： Jens KOWALSKY ,  Riteshkumar BHOJANI ,  Volker DUDEK

IPC: H01L29/861 ,  H01L29/20 ,  H01L29/36

Abstract: A semiconductor having a n-doped cathode layer, a p-doped anode layer, and a drift region, arranged between the cathode layer and the anode layer, with a dopant concentration of at most 8·1015 cm−3. The drift region has a lightly n-doped drift layer and a lightly p-doped drift layer, arranged between the n-doped drift layer and the anode layer, both drift layers each have a layer thickness of at least 5 μm. The cathode layer has a first section with a dopant concentration of at least 1·1017 cm−3 and a second section, arranged between the first section and the drift region, the second section has a layer thickness of at least 1 μm and a dopant concentration gradient that increases in the direction of the first section up to a dopant concentration maximum. The dopant concentration maximum is smaller or equal to the dopant concentration of the first section.

公开(公告)号：US10784381B2

公开(公告)日：2020-09-22

申请号：US16379008

申请日：2019-04-09

Applicant: 3-5 Power Electronics GmbH

Inventor： Volker Dudek

IPC: H01L29/861 ,  H01L29/34 ,  H01L29/06 ,  H01L29/20 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66 ,  H01L21/18

Abstract: A stacked III-V semiconductor component having a stack with a top, a bottom, a side surface, and a longitudinal axis. The stack has a p+ region, an n− layer, and an n+ region. The p+ region, the n− layer, and the n+ region follow one another in the specified order along the longitudinal axis and are monolithic in design, and include a GaAs compound. The n+ region or the p+ region is a substrate layer. The stack has, in the region of the side surface, a first and a second peripheral, shoulder-like edge. The first edge is composed of the substrate layer; the second edge is composed of the n− layer or of an intermediate layer adjacent to the n− layer and to the p+ region and the first and the second peripheral edges each have a width of at least 10 μm.

公开(公告)号：US10734532B2

公开(公告)日：2020-08-04

申请号：US16458789

申请日：2019-07-01

Applicant: 3-5 Power Electronics GmbH

Inventor： Volker Dudek

IPC: H01L29/861 ,  H01L33/02 ,  H01L33/30 ,  H01L29/20 ,  H01L29/36 ,  H01L29/32 ,  H01L29/66 ,  H01L29/872 ,  H01L21/18

Abstract: A stacked III-V semiconductor diode having an n+-layer with a dopant concentration of at least 1019 N/cm3, an n−-layer with a dopant concentration of 1012-1016 N/cm3, a layer thickness of 10-300 microns, a p+-layer with a dopant concentration of 5×1018-5×1020 cm3, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n+-layer or the p+-layer is formed as the substrate and a lower side of the n−-layer is materially bonded with an upper side of the n+-layer, and a doped intermediate layer is arranged between the n−-layer and the p+-layer and materially bonded with an upper side and a lower side.

公开(公告)号：US20190326446A1

公开(公告)日：2019-10-24

申请号：US16458789

申请日：2019-07-01

Applicant: 3-5 Power Electronics GmbH

Inventor： Volker Dudek

IPC: H01L29/861 ,  H01L21/18 ,  H01L29/20 ,  H01L29/36 ,  H01L29/32

Abstract: A stacked III-V semiconductor diode having an n+-layer with a dopant concentration of at least 1019 N/cm3, an n−-layer with a dopant concentration of 1012 -1016 N/cm3, a layer thickness of 10-300 microns, a p+-layer with a dopant concentration of 5×1018-5×1020 cm3, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n+-layer or the p+-layer is formed as the substrate and a lower side of the n−-layer is materially bonded with an upper side of the n+-layer, and a doped intermediate layer is arranged between the n−-layer and the p+-layer and materially bonded with an upper side and a lower side.