- 专利标题： VIA STRUCTURE WITH LOW RESISTIVITY AND METHOD FOR FORMING THE SAME
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申请号： US16163970申请日： 2018-10-18
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公开(公告)号： US20200058785A1公开(公告)日： 2020-02-20
- 发明人: Kuo-Chiang TSAI , Fu-Hsiang SU , Ke-Jing YU , Chih-Hong HWANG , Jyh-Huei CHEN
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsinchu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsinchu
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L29/66 ; H01L29/423 ; H01L23/522 ; H01L29/417 ; H01L21/48 ; H01L21/768
摘要：
A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.
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