公开(公告)号：US20200350416A1

公开(公告)日：2020-11-05

申请号：US16927953

申请日：2020-07-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chia-Ming HSU ,  Pei-Yu CHOU ,  Chih-Pin TSAO ,  Kuang-Yuan HSU ,  Jyh-Huei CHEN

IPC分类号： H01L29/45 ,  H01L23/485 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/8234 ,  H01L27/088

摘要： A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

公开(公告)号：US20200058785A1

公开(公告)日：2020-02-20

申请号：US16163970

申请日：2018-10-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Chiang TSAI ,  Fu-Hsiang SU ,  Ke-Jing YU ,  Chih-Hong HWANG ,  Jyh-Huei CHEN

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L23/522 ,  H01L29/417 ,  H01L21/48 ,  H01L21/768

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.

公开(公告)号：US20200321460A1

公开(公告)日：2020-10-08

申请号：US16907781

申请日：2020-06-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Chiang TSAI ,  Fu-Hsiang SU ,  Ke-Jing YU ,  Chih-Hong HWANG ,  Jyh-Huei CHEN

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522

摘要： A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.

公开(公告)号：US20200035605A1

公开(公告)日：2020-01-30

申请号：US16164054

申请日：2018-10-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Chiang TSAI ,  Jyh-Huei CHEN ,  Jye-Yen CHENG

IPC分类号： H01L23/538 ,  H01L29/417 ,  H01L23/532 ,  H01L21/768

摘要： Methods of fabricating an integrated circuit device are provided. The integrated circuit device includes a transistor formed on a substrate. The transistor includes a source region, a drain region, and a gate structure between the source region and the drain region. The integrated circuit device also includes a first dielectric layer over the transistor and a first via contact partially in the first dielectric layer and electrically connected to the source region. The integrated circuit device further includes a second via contact partially in the first dielectric layer and electrically connected to the gate structure. In addition, the upper portion of the first via contact and the upper portion of the second via contact protrude from the first dielectric layer.

公开(公告)号：US20170222008A1

公开(公告)日：2017-08-03

申请号：US15378574

申请日：2016-12-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chia-Ming HSU ,  Chih-Pin TSAO ,  Jyh-Huei CHEN ,  Kuang-Yuan HSU ,  Pei-Yu CHOU

IPC分类号： H01L29/45 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L21/3205

CPC分类号： H01L29/45 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823418 ,  H01L27/0886 ,  H01L29/665 ,  H01L29/7848

摘要： In a method of manufacturing a semiconductor device, a first contact hole is formed in one or more dielectric layers disposed over a source/drain region or a gate electrode. An adhesive layer is formed in the first contact hole. A first metal layer is formed on the adhesive layer in the first contact hole. A silicide layer is formed on an upper surface of the first metal layer. The silicide layer includes a same metal element as the first metal layer.

公开(公告)号：US20230085350A1

公开(公告)日：2023-03-16

申请号：US18057158

申请日：2022-11-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Chiang TSAI ,  Jyh-Huei CHEN

IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/522

摘要： In one example, a semiconductor device includes a first conductive feature embedded in a first dielectric layer such that a top surface of the first dielectric layer is higher than a top surface of first conductive feature, a contact etch stop layer (CESL) disposed on the first dielectric layer, and a second conductive feature embedded in a second dielectric layer. The second dielectric layer is disposed on the CESL and the second conductive feature extends through the CESL and is in direct contact with the first conductive feature.

公开(公告)号：US20200126843A1

公开(公告)日：2020-04-23

申请号：US16180913

申请日：2018-11-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Chiang TSAI ,  Fu-Hsiang SU ,  Ke-Jing YU ,  Jyh-Huei CHEN

IPC分类号： H01L21/768 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure laterally adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering the upper surface of the gate stack, a second insulating capping feature covering the upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from the material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.

公开(公告)号：US20200044072A1

公开(公告)日：2020-02-06

申请号：US16199906

申请日：2018-11-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Ho CHIANG ,  Cheng-Han WU ,  Jyh-Huei CHEN ,  Jhon-Jhy LIAW

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/66

摘要： A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure formed over the fin structure. The FinFET device structure also includes a contact formed over the fin structure and adjacent to the gate structure. The FinFET device structure further includes a first hard mask layer formed over the gate structure, and an upper portion of the first hard mask layer has an inverted-T shape. In addition, the FinFET device structure includes a second hard mask layer formed over the contact, and the second hard mask layer has a T shape.

公开(公告)号：US20170352559A1

公开(公告)日：2017-12-07

申请号：US15609199

申请日：2017-05-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Li-Jung LIU ,  Chih-Pin TSAO ,  Chia-Wei SOONG ,  Jyh-Huei CHEN ,  Shu-Hui WANG ,  Shih-Hsun CHANG

IPC分类号： H01L21/67 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/311 ,  H01J37/32

CPC分类号： H01L21/67069 ,  H01J37/32 ,  H01L21/0274 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/67063 ,  H01L23/485 ,  H01L29/7851 ,  H01L2924/12042

摘要： A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent. An example benefit includes reduction or elimination of diffusion of fluorine contaminants from a gate metal fill layer into its underlying layers and from conductive layers into diffusion barrier layers and silicide layers of source/drain contact structures and consequently, the reduction of the negative impact of these fluorine contaminants on device performance.