Invention Application
- Patent Title: DATA LATCH CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE
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Application No.: US16356980Application Date: 2019-03-18
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Publication No.: US20200090710A1Publication Date: 2020-03-19
- Inventor: Keisuke NAKATSUKA , Tomoya SANUKI , Takashi MAEDA , Go SHIKATA , Hideaki AOCHI
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Priority: JP2018-172343 20180914; JP2019-044614 20190312
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C7/08 ; G11C7/18 ; G11C16/26 ; H01L27/11529 ; H01L27/11573
Abstract:
A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.
Information query
