公开(公告)号：US20210090616A1

公开(公告)日：2021-03-25

申请号：US17109853

申请日：2020-12-02

Applicant: Toshiba Memory Corporation

Inventor： Keisuke NAKATSUKA ,  Tomoya SANUKI ,  Takashi MAEDA ,  Go SHIKATA ,  Hideaki AOCHI

IPC: G11C7/10 ,  G11C7/08 ,  H01L27/11573 ,  G11C16/26 ,  H01L27/11529 ,  G11C7/18

Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.

公开(公告)号：US20200090710A1

公开(公告)日：2020-03-19

申请号：US16356980

申请日：2019-03-18

Applicant: Toshiba Memory Corporation

Inventor： Keisuke NAKATSUKA ,  Tomoya SANUKI ,  Takashi MAEDA ,  Go SHIKATA ,  Hideaki AOCHI

IPC: G11C7/10 ,  G11C7/08 ,  G11C7/18 ,  G11C16/26 ,  H01L27/11529 ,  H01L27/11573

Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.

公开(公告)号：US20200020405A1

公开(公告)日：2020-01-16

申请号：US16579964

申请日：2019-09-24

Applicant: Toshiba Memory Corporation

Inventor： Takashi MAEDA

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/08 ,  G11C16/04

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

公开(公告)号：US20210295925A1

公开(公告)日：2021-09-23

申请号：US17340310

申请日：2021-06-07

Applicant: Toshiba Memory Corporation

Inventor： Takashi MAEDA

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

公开(公告)号：US20200303013A1

公开(公告)日：2020-09-24

申请号：US16896644

申请日：2020-06-09

Applicant: Toshiba Memory Corporation

Inventor： Takashi MAEDA

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

公开(公告)号：US20190156898A1

公开(公告)日：2019-05-23

申请号：US16260247

申请日：2019-01-29

Applicant: Toshiba Memory Corporation

Inventor： Takashi MAEDA

IPC: G11C16/16 ,  G11C16/14 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  H01L27/1157 ,  H01L27/11582

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

公开(公告)号：US20190006010A1

公开(公告)日：2019-01-03

申请号：US16122945

申请日：2018-09-06

Applicant: Toshiba Memory Corporation

Inventor： Takashi MAEDA

IPC: G11C16/16 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G11C5/14 ,  G11C16/30

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

公开(公告)号：US20180068732A1

公开(公告)日：2018-03-08

申请号：US15810489

申请日：2017-11-13

Applicant: Toshiba Memory Corporation

Inventor： Takashi MAEDA

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/16 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  H01L27/1157 ,  H01L27/11582

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.