公开(公告)号：US20200176061A1

公开(公告)日：2020-06-04

申请号：US16567629

申请日：2019-09-11

Applicant: Toshiba Memory Corporation

Inventor： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Naohito MOROZUMO ,  Go SHIKATA ,  Susumu FUJIMURA

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/24

Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.

公开(公告)号：US20190088663A1

公开(公告)日：2019-03-21

申请号：US15909369

申请日：2018-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Go SHIKATA ,  Yasuhiro SHIMURA

IPC: H01L27/1157 ,  G11C7/06 ,  G11C16/08 ,  G11C16/04 ,  G06F11/10 ,  G11C8/08

Abstract: A semiconductor memory device includes a first memory cell transistor, a second memory cell transistor, and a third memory cell transistor that are connected in series. A word line is coupled to a gate of the third memory cell transistor. A controller is configured to set a first upper limit value for voltages applied to the word line during writing of data to the first memory cell transistor and a second upper limit value for voltages applied to the word line during writing of data to the second memory cell transistor. The second upper limit value is different from the first upper limit value.

公开(公告)号：US20180277565A1

公开(公告)日：2018-09-27

申请号：US15909906

申请日：2018-03-01

Applicant: Toshiba Memory Corporation

Inventor： Takuya FUTATSUYAMA ,  Go SHIKATA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: H01L27/11582 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor memory device includes wirings arranged in parallel along a first direction, the wirings including first and second wirings that are adjacent and a third wiring adjacent to the second wiring, a first pillar between the first and second wirings and a second pillar between the second and third wirings, the first and second pillars each extending in a second direction crossing the first direction toward the semiconductor substrate, and first and second bit lines connected to the first and second pillars, respectively. A first voltage is applied to the second wiring during a program operation on a first memory cell at an intersection of the second wiring and the first pillar, and a second voltage higher than the first voltage is applied to the second wiring during a program operation on a second memory cell at an intersection of the second wiring and the second pillar.

公开(公告)号：US20210090616A1

公开(公告)日：2021-03-25

申请号：US17109853

申请日：2020-12-02

Applicant: Toshiba Memory Corporation

Inventor： Keisuke NAKATSUKA ,  Tomoya SANUKI ,  Takashi MAEDA ,  Go SHIKATA ,  Hideaki AOCHI

IPC: G11C7/10 ,  G11C7/08 ,  H01L27/11573 ,  G11C16/26 ,  H01L27/11529 ,  G11C7/18

Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.

公开(公告)号：US20210027843A1

公开(公告)日：2021-01-28

申请号：US17068609

申请日：2020-10-12

Applicant: Toshiba Memory Corporation

Inventor： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Naohito MOROZUMI ,  Go SHIKATA ,  Susumu FUJIMURA

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/24

Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.

公开(公告)号：US20200090710A1

公开(公告)日：2020-03-19

申请号：US16356980

申请日：2019-03-18

Applicant: Toshiba Memory Corporation

Inventor： Keisuke NAKATSUKA ,  Tomoya SANUKI ,  Takashi MAEDA ,  Go SHIKATA ,  Hideaki AOCHI

IPC: G11C7/10 ,  G11C7/08 ,  G11C7/18 ,  G11C16/26 ,  H01L27/11529 ,  H01L27/11573

Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.