Semiconductor structures are provided. A memory cell includes a latch circuit formed by two cross-coupled inverters and a pass-gate transistor coupling an output of the latch circuit to a bit line. Each cross-coupled inverter is connected to a VDD line of a first metallization layer. A word line of a second metallization layer is connected to a gate of the pass-gate transistor through a first via over the gate of the pass-gate transistor, a first landing pad of the first metallization layer, and a second via over the first landing pad. A source/drain region of the pass-gate transistor is connected to the bit line of a third metallization layer through a contact over the source/drain region, a third via over the contact, a continuous via-plug over the third via, and a fourth via over the continuous via-plug. The continuous via-plug penetrates the first and second metallization layers.