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    INTEGRATED CIRCUIT STRUCTURE
    1.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE 有权

    公开(公告)号：US20210313323A1

    公开(公告)日：2021-10-07

    申请号：US17353552

    申请日：2021-06-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jhon-Jhy LIAW

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/02

    Abstract: An IC structure comprises first, second, and third circuits. The first circuit comprises a first semiconductor fin, a first gate electrode extending across the first semiconductor fin, and a first gate dielectric layer spacing the first gate electrode apart from the first semiconductor fin. The second circuit comprises a second semiconductor fin, a second gate electrode extending across the second semiconductor fin, and a second gate dielectric layer spacing the second gate electrode apart from the second semiconductor fin. The third circuit comprises a third semiconductor fin, a third gate electrode extending across the third semiconductor fin, and a third gate dielectric layer spacing the third gate electrode apart from the third semiconductor fin. The first gate dielectric layer has a greater thickness than the second gate dielectric layer. The third semiconductor fin has a smaller width than the second semiconductor fin.

    IC INCLUDING STANDARD CELLS AND SRAM CELLS
    3.
    发明申请
    IC INCLUDING STANDARD CELLS AND SRAM CELLS 有权

    公开(公告)号：US20210057281A1

    公开(公告)日：2021-02-25

    申请号：US16548285

    申请日：2019-08-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jhon-Jhy LIAW

    IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/8239

    Abstract: An IC is provided. The IC includes a plurality of P-type gate-all-around (GAA) field-effect transistors (FETs). At least one first P-type GAA FET includes a plurality of silicon (Si) channel regions vertically stacked over an N-type well region. At least one second P-type GAA FET includes a plurality of silicon germanium (SiGe) channel regions vertically stacked over the N-type well region.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200051906A1

    公开(公告)日：2020-02-13

    申请号：US16101566

    申请日：2018-08-13

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jhon-Jhy LIAW

    IPC: H01L23/522 ,  H01L23/532 ,  H01L27/092 ,  H01L21/768

    Abstract: A semiconductor device includes a semiconductor substrate, a metal layer, a dielectric layer, and a via. The metal layer is disposed above the semiconductor substrate. The dielectric layer is disposed between the metal layer and the semiconductor substrate. The via is embedded in the dielectric layer and comprises a first portion and a second portion between the first portion and the semiconductor substrate. The first portion of the via has a first width. The second portion of the via has a second width greater than the first width of the first portion.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190288069A1

    公开(公告)日：2019-09-19

    申请号：US15925630

    申请日：2018-03-19

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jhon-Jhy LIAW

    IPC: H01L29/08 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/11

    Abstract: A semiconductor device includes a substrate, a first circuit, and a second circuit. The first circuit is disposed on the substrate and includes a first semiconductor fin and a first gate electrode straddling the first semiconductor fin. The second circuit is different from the first circuit and disposed on the substrate. The second circuit includes a second semiconductor fin and a second gate electrode straddling the second semiconductor fin. A width of the first semiconductor fin is different from a width of the second semiconductor fin.

    SEMICONDUCTOR MEMORY WITH DATA LINE CAPACITIVE COUPLING
    8.
    发明申请
    SEMICONDUCTOR MEMORY WITH DATA LINE CAPACITIVE COUPLING 有权

    公开(公告)号：US20170162256A1

    公开(公告)日：2017-06-08

    申请号：US15435149

    申请日：2017-02-16

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jhon-Jhy LIAW

    IPC: G11C11/00

    CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/00 ,  G11C11/412 ,  G11C11/4125

    Abstract: A semiconductor memory includes a first data line, a second data line, a first coupling line, a second coupling line, a first plurality of transistors, and a second plurality of transistors. The first coupling line is configured to be capacitively coupled with the first data line. The second coupling line is configured to be capacitively coupled with the second data line. The first plurality of transistors are configured to transmit a first voltage to the first coupling line and the second coupling line in response to a first control signal. The second plurality of transistors are configured to transmit a second voltage to the first coupling line, the second coupling line, or a combination thereof in response to a second control signal and a third control signal.

    MEMORY DEVICES WITH STRAP CELLS
    9.
    发明申请
    MEMORY DEVICES WITH STRAP CELLS 有权
    具有条纹细胞的记忆装置

    公开(公告)号：US20170076755A1

    公开(公告)日：2017-03-16

    申请号：US15153687

    申请日：2016-05-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jonathan Tsung-Yung CHANG ,  Cheng-Hung LEE ,  Chi-Ting CHENG ,  Hung-Jen LIAO ,  Jhon-Jhy LIAW ,  Yen-Huei CHEN

    IPC: G11C5/02 ,  G11C7/22 ,  G11C7/10 ,  G11C5/14

    CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/14 ,  G11C7/10 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/417

    Abstract: A device includes a memory array, a first data line, and a second data line. The memory array includes a first strap cell, a first sub-bank, and a second sub-bank, in which the first strap cell is disposed between the first sub-bank and the second sub-bank. The first data line has a first portion and a second portion, in which the first portion of the first data line is disconnected from the second portion of the first data line, and the second portion of the first data line is configured to couple the first sub-bank to a first input/output (I/O) circuit. The second data line and the first portion of the first data line are configured to couple the second sub-bank to the first I/O circuit.

    Abstract translation: 一种设备包括存储器阵列，第一数据线和第二数据线。 存储器阵列包括第一带单元，第一子库和第二子库，其中第一带单元设置在第一子库和第二子库之间。 第一数据线具有第一部分和第二部分，其中第一数据线的第一部分与第一数据线的第二部分断开，并且第一数据线的第二部分被配置为将第一数据线的第一部分耦合第一数据线 子行到第一个输入/输出（I / O）电路。 第二数据线和第一数据线的第一部分被配置为将第二子组耦合到第一I / O电路。

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