Invention Application
- Patent Title: MULTIPLE MEMORY DEVICES HAVING PARITY PROTECTION
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Application No.: US16155573Application Date: 2018-10-09
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Publication No.: US20200110661A1Publication Date: 2020-04-09
- Inventor: Harish Reddy Singidi , Xiangang Luo , Preston Thomson , Michael G. McNeeley
- Applicant: Micron Technology, Inc.
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G11C29/52 ; G06F3/06

Abstract:
A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.
Public/Granted literature
- US10789126B2 Multiple memory devices having parity protection Public/Granted day:2020-09-29
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