公开(公告)号：US20190066792A1

公开(公告)日：2019-02-28

申请号：US15690920

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath Ratnam ,  Preston Thomson ,  Harish Singidi ,  Jung Sheng Hoei ,  Peter Sean Feeley ,  Jianmin Huang

IPC: G11C16/10 ,  G11C16/22

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/20 ,  G11C16/22 ,  G11C16/28 ,  G11C16/3418 ,  G11C29/021 ,  G11C29/028 ,  G11C2211/5641

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

公开(公告)号：US11101015B2

公开(公告)日：2021-08-24

申请号：US16222295

申请日：2018-12-17

Applicant: Micron Technology, Inc.

Inventor： Aswin Thiruvengadam ,  Sivagnanam Parthasarathy ,  Preston Thomson

IPC: G11C29/38 ,  G11C29/36 ,  G06F11/263

Abstract: A target vector representing a usage parameter corresponding to a test of a memory component is generated. A test sample is assigned to the target vector and a set of path variables are generated for the test sample. A test process of the test is executed using the test sample in accordance with the set of path variables to generate a test result. A failure associated with the test result is identified.

公开(公告)号：US20200110661A1

公开(公告)日：2020-04-09

申请号：US16155573

申请日：2018-10-09

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Xiangang Luo ,  Preston Thomson ,  Michael G. McNeeley

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10354732B2

公开(公告)日：2019-07-16

申请号：US15690920

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath Ratnam ,  Preston Thomson ,  Harish Singidi ,  Jung Sheng Hoei ,  Peter Sean Feeley ,  Jianmin Huang

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/22

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

公开(公告)号：US10096380B1

公开(公告)日：2018-10-09

申请号：US15692962

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Scott Anthony Stoller ,  Preston Thomson ,  Devin Batutis ,  Harish Singidi ,  Kulachet Tanpairoj

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/44 ,  G06F11/07

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.

公开(公告)号：US10789126B2

公开(公告)日：2020-09-29

申请号：US16155573

申请日：2018-10-09

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Xiangang Luo ,  Preston Thomson ,  Michael G. McNeeley

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10522229B2

公开(公告)日：2019-12-31

申请号：US15691584

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Singidi ,  Jianmin Huang ,  Preston Thomson ,  Sebastien Andre Jean

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/11556

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US10360947B2

公开(公告)日：2019-07-23

申请号：US15692508

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Tyson M. Stichka ,  Preston Thomson ,  Scott Anthony Stoller ,  Christopher Bueb ,  Jianmin Huang ,  Kulachet Tanpairoj ,  Harish Singidi

IPC: G11C16/06 ,  G11C5/00 ,  G11C16/26 ,  G11C16/04 ,  G11C7/04

Abstract: Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.

公开(公告)号：US10387281B2

公开(公告)日：2019-08-20

申请号：US15690903

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Giuseppe Cariello ,  Deping He ,  Scott Anthony Stoller ,  Devin Batutis ,  Preston Thomson

IPC: G06F11/20

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.

公开(公告)号：US10325670B2

公开(公告)日：2019-06-18

申请号：US16129422

申请日：2018-09-12

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Scott Anthony Stoller ,  Preston Thomson ,  Devin Batutis ,  Harish Reddy Singidi ,  Kulachet Tanpairoj

IPC: G11C29/00 ,  G11C29/38 ,  G06F11/07 ,  G11C29/44

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.