Invention Application
- Patent Title: VERTICALLY STACKED NANOSHEET CMOS TRANSISTOR
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Application No.: US16156391Application Date: 2018-10-10
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Publication No.: US20200118891A1Publication Date: 2020-04-16
- Inventor: Kangguo Cheng , JUNTAO LI , ZHENXING BI
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L27/12

Abstract:
Embodiments of the present invention are directed to techniques for generating vertically stacked nanosheet CMOS (Complementary Metal Oxide Semiconductor) transistor architectures. In a non-limiting embodiment of the invention, a first rare earth oxide layer is formed over a substrate. An n-FET nanosheet stack is formed on the rare earth oxide layer. The n-FET nanosheet stack includes a first nanosheet. A second rare earth oxide layer is formed on the n-FET nanosheet stack. A p-FET nanosheet stack is formed on the second rare earth oxide layer. The p-FET nanosheet stack includes a second nanosheet.
Public/Granted literature
- US10741456B2 Vertically stacked nanosheet CMOS transistor Public/Granted day:2020-08-11
Information query
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