公开(公告)号：US20180368756A1

公开(公告)日：2018-12-27

申请号：US15631064

申请日：2017-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： MAHMOUD AMIN ,  ZHENXING BI ,  LAWRENCE A. CLEVENGER ,  LEIGH ANNE H. CLEVENGER ,  KRISHNA R. TUNGA

IPC: A61B5/00 ,  G06F19/00

Abstract: Embodiments of the invention are directed to a computer-implemented method for generating a sleep optimization plan. A non-limiting example of the computer-implemented method includes receiving, by a processor, genetic data for a user. The method also includes receiving, by the processor, Internet of Things (IoT) device data for the user. The method also includes generating, by the processor, a sleep duration measurement for the user based at last in part upon the IoT device data. The method also includes generating, by the processor, a sleep optimization plan for the user based at least in part upon the genetic data.

公开(公告)号：US20180082953A1

公开(公告)日：2018-03-22

申请号：US15268025

申请日：2016-09-16

Applicant: International Business Machines Corporation

Inventor： ZHENXING BI ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L29/08

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/456

Abstract: A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials.

公开(公告)号：US20200135893A1

公开(公告)日：2020-04-30

申请号：US16169388

申请日：2018-10-24

Applicant: International Business Machines Corporation

Inventor： ZHENXING BI ,  Kangguo Cheng ,  YONGAN Xu ,  Yi Song

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/768 ,  H01L29/51 ,  H01L29/06 ,  H01L21/762

Abstract: Embodiments of the present invention are directed to techniques for forming a vertical field effect transistor (VFET) top spacer using an area selective cyclic deposition. In a non-limiting embodiment of the invention, a first semiconductor fin is formed over a substrate. A second semiconductor fin is formed over the substrate and adjacent to the first semiconductor fin. A dielectric isolation region is formed between the first semiconductor fin and the second semiconductor fin. A top spacer is formed between the first semiconductor fin and the second semiconductor fin by cyclically depositing dielectric layers over the dielectric isolation region. The dielectric layers are inhibited from depositing on a surface of the first semiconductor fin and on a surface of the second semiconductor fin during the cyclic deposition process.

公开(公告)号：US20200118891A1

公开(公告)日：2020-04-16

申请号：US16156391

申请日：2018-10-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  JUNTAO LI ,  ZHENXING BI

IPC: H01L21/84 ,  H01L27/12

Abstract: Embodiments of the present invention are directed to techniques for generating vertically stacked nanosheet CMOS (Complementary Metal Oxide Semiconductor) transistor architectures. In a non-limiting embodiment of the invention, a first rare earth oxide layer is formed over a substrate. An n-FET nanosheet stack is formed on the rare earth oxide layer. The n-FET nanosheet stack includes a first nanosheet. A second rare earth oxide layer is formed on the n-FET nanosheet stack. A p-FET nanosheet stack is formed on the second rare earth oxide layer. The p-FET nanosheet stack includes a second nanosheet.

公开(公告)号：US20200090542A1

公开(公告)日：2020-03-19

申请号：US16134164

申请日：2018-09-18

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Stefania Axo ,  Leigh Anne H. Clevenger ,  Krishna R. Tunga ,  MAHMOUD AMIN ,  Bryan Gury ,  Christopher J. Penny ,  Mark C. Wallen ,  ZHENXING BI ,  Yang Liu

IPC: G09B19/00 ,  G06N99/00 ,  G06F9/451 ,  G09B5/06 ,  G06F3/0481

Abstract: A computer system interacts with a user with a behavioral state. An activity performed by an entity with a behavioral state is determined. A virtual character corresponding to the entity and performing the determined activity of the entity is generated and displayed. A mental state of the entity responsive to the virtual character is detected. In response to detection of a positive mental state of the entity, one or more natural language terms are provided to the entity corresponding to the activity performed by the virtual character. Embodiments of the present invention further include a method and program product for interacting with a user with a behavioral state in substantially the same manner described above.

公开(公告)号：US20200066882A1

公开(公告)日：2020-02-27

申请号：US16666590

申请日：2019-10-29

Applicant: International Business Machines Corporation

Inventor： ZHENXING BI ,  Kangguo Cheng ,  JUNTAO LI ,  PENG XU

IPC: H01L29/66 ,  H01L23/522 ,  H01L21/768 ,  H01L27/112 ,  H01L27/11582 ,  H01L21/311 ,  H01L29/417 ,  H01L29/78 ,  H01L29/08

Abstract: A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner.

公开(公告)号：US20200161303A1

公开(公告)日：2020-05-21

申请号：US16691732

申请日：2019-11-22

Applicant: International Business Machines Corporation

Inventor： ZHENXING BI ,  Kangguo CHENG ,  ZHENG XU ,  DEXIN KONG

IPC: H01L27/092 ,  H01L29/20 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/033 ,  H01L29/08 ,  H01L29/66

Abstract: An integrated semiconductor device includes a substrate, a first vertical transistor, and a second vertical transistor. The substrate has a first substrate region and a second substrate region. The first vertical transistor is disposed on the substrate in the first substrate region. The first vertical transistor is n-type field-effect vertical transistor (n-VFET) with a first channel crystalline orientation. The second vertical transistor is disposed on the substrate in the second substrate region. The second vertical transistor is p-type field-effect vertical transistor (p-VFET) with a second channel crystalline orientation. The first channel crystalline orientation is different from the second channel orientation. A common bottom source and drain region as well as common bottom and top spacers regions are provided for the first vertical transistor and the second vertical transistor.

公开(公告)号：US20200161302A1

公开(公告)日：2020-05-21

申请号：US16192896

申请日：2018-11-16

Applicant: International Business Machines Corporation

Inventor： ZHENXING BI ,  Kangguo CHENG ,  ZHENG XU ,  DEXIN KONG

IPC: H01L27/092 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/033 ,  H01L21/8238

Abstract: An integrated semiconductor device includes a substrate, a first vertical transistor, and a second vertical transistor. The substrate has a first substrate region and a second substrate region. The first vertical transistor is disposed on the substrate in the first substrate region. The first vertical transistor is n-type field-effect vertical transistor (n-VFET) with a first channel crystalline orientation. The second vertical transistor is disposed on the substrate in the second substrate region. The second vertical transistor is p-type field-effect vertical transistor (p-VFET) with a second channel crystalline orientation. The first channel crystalline orientation is different from the second channel orientation. A common bottom source and drain region as well as common bottom and top spacers regions are provided for the first vertical transistor and the second vertical transistor.