A memory device includes a memory cell array in which plural memory cells are arranged in a matrix manner, and a mode selection part. The mode selection part has at least any two of a first mode, a second mode, a third mode and selects any operation mode. The first mode is for reading and writing 1-bit data with the first memory cell or the second memory cell. The second mode is for reading and writing the 1-bit data with a cell unit including the N first memory cells and the N second memory cells connected to a bit line pair. The third mode is for reading and writing the 1-bit data with a cell unit including the M first memory cells and the M second memory cells connected to the bit line pair. M and N are 1 or more integers which are different from each other.