A gate driving circuit includes: a plurality of stages, a k-th stage from among the plurality of stages, the k-th stage including: an input circuit to receive a previous carry signal and to pre-charge a first node; a first output circuit to output a k-th gate signal; a second output circuit to output a k-th carry signal; a discharge hold circuit to transmit a clock signal to a second node, and to discharge the second node with a second low voltage; a first pull down circuit to discharge the k-th gate signal with a first low voltage, and to discharge the first node and the k-th carry signal with the second low voltage; and a discharge circuit for discharging the k-th carry signal with the second low voltage in response to the previous carry signal.