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公开(公告)号：US10573244B2
公开(公告)日：2020-02-25
申请号：US15335210
申请日：2016-10-26
发明人： Jaehoon Lee , Bonghyun You , Soo-yeon Lee , Seokha Hong
IPC分类号： G09G3/32 , G09G3/3266
摘要： A gate driving circuit includes: a plurality of stages, a k-th stage from among the plurality of stages, the k-th stage including: an input circuit to receive a previous carry signal and to pre-charge a first node; a first output circuit to output a k-th gate signal; a second output circuit to output a k-th carry signal; a discharge hold circuit to transmit a clock signal to a second node, and to discharge the second node with a second low voltage; a first pull down circuit to discharge the k-th gate signal with a first low voltage, and to discharge the first node and the k-th carry signal with the second low voltage; and a discharge circuit for discharging the k-th carry signal with the second low voltage in response to the previous carry signal.
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公开(公告)号：US10170029B2
公开(公告)日：2019-01-01
申请号：US15139196
申请日：2016-04-26
发明人： Bonghyun You , Seokha Hong , Soo-yeon Lee
摘要： A display device includes: a display panel; a voltage generator to output a gate on voltage to a voltage output terminal; a clock generator to receive the gate on voltage to generate at least one clock signal; a gate driving circuit including a plurality of driving stages to output gate signals to gate lines in response to the at least one clock signal, each of the driving stages including at least one transistor to adjust a threshold voltage based on a back bias control voltage; and a signal controller to detect a current variation of the voltage output terminal and including a back bias controller to search for the back bias control voltage to minimize a consumption current level of the voltage output terminal while changing the back bias control voltage from a default voltage level when the detected current variation is greater than a reference level.
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3.发明申请公开(公告)号：US20170069283A1
公开(公告)日：2017-03-09
申请号：US15139196
申请日：2016-04-26
发明人： Bonghyun You , Seokha Hong , Soo-yeon Lee
IPC分类号： G09G3/36
CPC分类号： G09G3/2022 , G09G3/2092 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G11C19/184
摘要： A display device includes: a display panel; a voltage generator to output a gate on voltage to a voltage output terminal; a clock generator to receive the gate on voltage to generate at least one clock signal; a gate driving circuit including a plurality of driving stages to output gate signals to gate lines in response to the at least one clock signal, each of the driving stages including at least one transistor to adjust a threshold voltage based on a back bias control voltage; and a signal controller to detect a current variation of the voltage output terminal and including a back bias controller to search for the back bias control voltage to minimize a consumption current level of the voltage output terminal while changing the back bias control voltage from a default voltage level when the detected current variation is greater than a reference level.
摘要翻译： 显示装置包括：显示面板; 电压发生器，用于将电压输入到电压输出端子; 时钟发生器，用于接收栅极导通电压以产生至少一个时钟信号; 栅极驱动电路，其包括多个驱动级，以响应于所述至少一个时钟信号将栅极信号输出到栅极线，每个驱动级包括至少一个晶体管，以基于反向偏置控制电压来调节阈值电压; 以及信号控制器，用于检测电压输出端子的电流变化并且包括反向偏置控制器以搜索反向偏置控制电压，以使电压输出端子的消耗电流电平最小化，同时将偏置控制电压从默认电压 当检测到的电流变化大于参考电平时。
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公开(公告)号：US10930211B2
公开(公告)日：2021-02-23
申请号：US16235374
申请日：2018-12-28
发明人： Jai-hyun Koh , Jaehoon Lee , Heendol Kim , Kuk-hwan Ahn , Soo-yeon Lee , Moonshik Kang
IPC分类号： G09G3/3233 , G09G3/36 , G09G3/34 , G09G3/3225
摘要： A luminance control circuit of a display device includes a target luminance gain calculator calculating a target luminance gain based on an average luminance of a first image signal when the first image signal is determined to be a still image, an output luminance gain calculator calculating an output luminance gain based on a previous output luminance gain of a previous frame and the target luminance gain of a present frame, and a luminance scaler outputting a second image signal obtained by changing a luminance of the first image signal based on the output luminance gain.
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公开(公告)号：US20200184899A1
公开(公告)日：2020-06-11
申请号：US16790655
申请日：2020-02-13
发明人： Jaehoon Lee , Bonghyun You , Soo-yeon Lee , Seokha Hong
IPC分类号： G09G3/3266 , G11C19/28 , G09G3/36
摘要： A gate driving circuit includes: a plurality of stages, a k-th stage from among the plurality of stages, the k-th stage including: an input circuit to receive a previous carry signal and to pre-charge a first node; a first output circuit to output a k-th gate signal; a second output circuit to output a k-th carry signal; a discharge hold circuit to transmit a clock signal to a second node, and to discharge the second node with a second low voltage; a first pull down circuit to discharge the k-th gate signal with a first low voltage, and to discharge the first node and the k-th carry signal with the second low voltage; and a discharge circuit for discharging the k-th carry signal with the second low voltage in response to the previous carry signal.
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公开(公告)号：US20170301279A1
公开(公告)日：2017-10-19
申请号：US15335210
申请日：2016-10-26
发明人： Jaehoon Lee , Bonghyun You , Soo-yeon Lee , Seokha Hong
IPC分类号： G09G3/20
CPC分类号： G09G3/3266 , G09G3/3677 , G09G2310/0286 , G11C19/28
摘要： A gate driving circuit includes: a plurality of stages, a k-th stage from among the plurality of stages, the k-th stage including: an input circuit to receive a previous carry signal and to pre-charge a first node; a first output circuit to output a k-th gate signal; a second output circuit to output a k-th carry signal; a discharge hold circuit to transmit a clock signal to a second node, and to discharge the second node with a second low voltage; a first pull down circuit to discharge the k-th gate signal with a first low voltage, and to discharge the first node and the k-th carry signal with the second low voltage; and a discharge circuit for discharging the k-th carry signal with the second low voltage in response to the previous carry signal.
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公开(公告)号：US11222595B2
公开(公告)日：2022-01-11
申请号：US16790655
申请日：2020-02-13
发明人： Jaehoon Lee , Bonghyun You , Soo-yeon Lee , Seokha Hong
IPC分类号： G09G3/3266 , G09G3/36 , G11C19/28
摘要： A gate driving circuit includes: a plurality of stages, a k-th stage from among the plurality of stages, the k-th stage including: an input circuit to receive a previous carry signal and to pre-charge a first node; a first output circuit to output a k-th gate signal; a second output circuit to output a k-th carry signal; a discharge hold circuit to transmit a clock signal to a second node, and to discharge the second node with a second low voltage; a first pull down circuit to discharge the k-th gate signal with a first low voltage, and to discharge the first node and the k-th carry signal with the second low voltage; and a discharge circuit for discharging the k-th carry signal with the second low voltage in response to the previous carry signal.
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