Invention Application
- Patent Title: CLOCK JITTER MEASUREMENT USING SIGNAL-TO-NOISE RATIO DEGRADATION IN A CONTINUOUS TIME DELTA-SIGMA MODULATOR
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Application No.: US16702246Application Date: 2019-12-03
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Publication No.: US20200186162A1Publication Date: 2020-06-11
- Inventor: Ankur BAL , Rupesh SINGH
- Applicant: STMicroelectronics International N.V.
- Applicant Address: NL Schiphol
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Schiphol
- Main IPC: H03M3/00
- IPC: H03M3/00 ; H03K3/037 ; G06F1/10

Abstract:
A continuous time Delta-Sigma (CT-ΔΣ) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-ΔΣ modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-ΔΣ modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.
Public/Granted literature
- US10862503B2 Clock jitter measurement using signal-to-noise ratio degradation in a continuous time delta-sigma modulator Public/Granted day:2020-12-08
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