Invention Application
- Patent Title: STACKED TRANSISTORS WITH DIELECTRIC BETWEEN CHANNELS OF DIFFERENT DEVICE STRATA
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Application No.: US16279693Application Date: 2019-02-19
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Publication No.: US20200266218A1Publication Date: 2020-08-20
- Inventor: Aaron D. Lilak , Gilbert W. Dewey , Willy Rachmady , Rishabh Mehandru , Ehren Mannebach , Cheng-Ying Huang , Anh Phan , Patrick Morrow , Kimin Jun
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/84
Abstract:
Disclosed herein are stacked transistors with dielectric between channel materials, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate dielectric.
Public/Granted literature
- US11552104B2 Stacked transistors with dielectric between channels of different device strata Public/Granted day:2023-01-10
Information query
IPC分类:
