Invention Application
- Patent Title: PROTECTING AN INTEGRATED CIRCUIT FROM THE DRILLING OF A SOURCE AND/OR DRAIN CONTACT
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Application No.: US16926128Application Date: 2020-07-10
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Publication No.: US20210020663A1Publication Date: 2021-01-21
- Inventor: Philippe GALY , Thomas BEDECARRATS
- Applicant: STMicroelectronics SA
- Applicant Address: FR Montrouge
- Assignee: STMicroelectronics SA
- Current Assignee: STMicroelectronics SA
- Current Assignee Address: FR Montrouge
- Priority: FR1907925 20190715
- Main IPC: H01L27/12
- IPC: H01L27/12

Abstract:
An integrated circuit includes a MOS transistor that is located in and on a semiconductor film of a silicon-on-insulator (SOI) substrate. The SOI substrate has, below a buried insulator layer, a first back gate region and two first auxiliary regions that are located, respectively, below source and drain contact regions of the MOS transistor. The conductivity type of the two first auxiliary regions is the opposite the conductivity type of the first back gate region. The conductivity type of the two first auxiliary regions is identical to the conductivity type of the source and drain contact regions of the MOS transistor.
Information query
IPC分类: