公开(公告)号：US20230268338A1

公开(公告)日：2023-08-24

申请号：US18096160

申请日：2023-01-12

Applicant: STMicroelectronics SA

Inventor： Philippe GALY

IPC: H01L27/02

CPC classification number: H01L27/0274 ,  H01L27/0255

Abstract: An electrostatic discharge protection device is formed using only electrically connected transistors. The transistors include: a first MOS-type transistor forming a clamping circuit coupled between first and second supply nodes; a second MOS-type transistor coupled between the first supply node and a gate terminal of the first MOS-type transistor; and a third MOS-type transistor having a first gate terminal coupled to a gate terminal of the second MOS-type transistor, a second gate terminal coupled to one of the first and second supply nodes, and first and second conduction terminals coupled to the second supply node.

公开(公告)号：US20200097036A1

公开(公告)日：2020-03-26

申请号：US16572130

申请日：2019-09-16

Applicant: STMicroelectronics SA

Inventor： Renan LETHIECQ ,  Philippe GALY

IPC: G05F3/24 ,  G01K7/25

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

公开(公告)号：US20130264677A1

公开(公告)日：2013-10-10

申请号：US13859418

申请日：2013-04-09

Applicant: STMICROELECTRONICS SA

Inventor： Philippe GALY ,  Jean JIMENEZ

IPC: H01L27/02 ,  H01L21/77

CPC classification number: H01L27/0207 ,  H01L21/76264 ,  H01L21/77 ,  H01L27/088 ,  H01L27/1211 ,  H01L29/0692 ,  H01L29/435 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7825

Abstract: At least three electrically conducting blocks are disposed within an isolating region; and at least two of them are mutually separated and capacitively coupled by a part of the isolating region. At least two of them, being semiconductor, have opposite types of conductivity or identical types of conductivity, but with different concentrations of dopants, and these are in mutual contact by one of their sides. The mutual arrangement of these blocks within the isolating region, their type of conductivity and their concentration of dopants form at least one electronic module. Some of the blocks define input and output blocks.

Abstract translation: 至少三个导电块设置在隔离区内; 并且它们中的至少两个被隔离区域的一部分相互分离和电容耦合。 它们中的至少两个是半导体，具有相反的导电性或相同类型的导电性，但是具有不同浓度的掺杂剂，并且这些掺杂物的两侧之间相互接触。 这些块在隔离区域内的相互排列，它们的导电类型及其掺杂剂的浓度形成至少一个电子模块。 一些块定义输入和输出块。

公开(公告)号：US20220384419A1

公开(公告)日：2022-12-01

申请号：US17748311

申请日：2022-05-19

Applicant: STMicroelectronics SA

Inventor： Philippe GALY

IPC: H01L27/02 ,  H01L23/66

Abstract: An integrated circuit is formed by a semiconductor part with a semiconductor substrate and an interconnection part including levels of metals. An electrostatic-discharge sensor includes a semiconductor structure in the semiconductor part and a network of metal antennas in the interconnection part. The electrostatic-discharge sensor has at least one pair of two nodes having one of a resistive link or a capacitive link or a PN-junction link in the semiconductor structure. The antennas of the network of antennas coupled to the nodes of the least one pair of two nodes exhibit an asymmetry in one or more of shape and size.

公开(公告)号：US20210390374A1

公开(公告)日：2021-12-16

申请号：US17347374

申请日：2021-06-14

Applicant: STMICROELECTRONICS SA

Inventor： Valerian CINCON ,  Philippe GALY

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: A method includes generating, by a first spiking neuron, an event detection signal indicating a time of detection of an event in a data flow. The event detection signal is transmitted from the first spiking neuron to a second spiking neuron. The second spiking neuron generates a spike delayed, with respect to the time of detection of the event, according to an amplitude of the event. The delayed spike is included in a coded signal.

公开(公告)号：US20190288079A1

公开(公告)日：2019-09-19

申请号：US16434920

申请日：2019-06-07

Applicant: STMicroelectronics SA

Inventor： Sotirios ATHANASIOU ,  Philippe GALY

IPC: H01L29/36 ,  H01L29/786

Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.

公开(公告)号：US20210278286A1

公开(公告)日：2021-09-09

申请号：US17192411

申请日：2021-03-04

Applicant: STMicroelectronics SA

Inventor： Philippe GALY ,  Renan LETHIECQ

IPC: G01K7/01 ,  G01K7/22 ,  H01C7/04

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

公开(公告)号：US20210020660A1

公开(公告)日：2021-01-21

申请号：US16927510

申请日：2020-07-13

Applicant: STMicroelectronics SA

Inventor： Thomas BEDECARRATS ,  Philippe GALY

IPC: H01L27/12

Abstract: A silicon-on-insulator semiconductor substrate supports rows extending in a direction. Each row includes complementary MOS transistors and associated contact regions allowing back gate of the complementary MOS transistors to be biased. All transistors and associated contact regions of a given row are mutually isolated by a first trench isolation. Each row is bordered on opposed edges extending parallel to said direction by corresponding second trench isolations that are shallower than the first trench isolation.

公开(公告)号：US20200373965A1

公开(公告)日：2020-11-26

申请号：US16878084

申请日：2020-05-19

Applicant: STMicroelectronics SA

Inventor： Mohammed TMIMI ,  Philippe GALY

IPC: H04B3/02 ,  H04L27/20

Abstract: Binary data is processed through a differential pre-encoder, which includes a simple modulo-2 addition. This step is used to cancel the propagation error that can be introduced by duo-binary modulation and to simplify demodulation. Next the duo-binary encoder introduces controlled Inter Symbol Interference between a previously sent bit and a present bit to compress the spectral density closer to the DC. Next a 60-GHz carrier is modulated and transmitted over differential transmission lines.

公开(公告)号：US20200006320A1

公开(公告)日：2020-01-02

申请号：US16454230

申请日：2019-06-27

Applicant: STMicroelectronics SA

Inventor： Thomas BEDECARRATS ,  Louise DE CONTI ,  Philippe GALY

IPC: H01L27/02

Abstract: A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device.