公开(公告)号：US20210020660A1

公开(公告)日：2021-01-21

申请号：US16927510

申请日：2020-07-13

Applicant: STMicroelectronics SA

Inventor： Thomas BEDECARRATS ,  Philippe GALY

IPC: H01L27/12

Abstract: A silicon-on-insulator semiconductor substrate supports rows extending in a direction. Each row includes complementary MOS transistors and associated contact regions allowing back gate of the complementary MOS transistors to be biased. All transistors and associated contact regions of a given row are mutually isolated by a first trench isolation. Each row is bordered on opposed edges extending parallel to said direction by corresponding second trench isolations that are shallower than the first trench isolation.

公开(公告)号：US20200006320A1

公开(公告)日：2020-01-02

申请号：US16454230

申请日：2019-06-27

Applicant: STMicroelectronics SA

Inventor： Thomas BEDECARRATS ,  Louise DE CONTI ,  Philippe GALY

IPC: H01L27/02

Abstract: A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device.

公开(公告)号：US20220138530A1

公开(公告)日：2022-05-05

申请号：US17572899

申请日：2022-01-11

Applicant: STMicroelectronics SA

Inventor： Philippe GALY ,  Thomas BEDECARRATS

IPC: G06N3/04 ,  G06N3/063 ,  H01L27/02 ,  G11C11/54

Abstract: An artificial-neuron device includes an integration-generation circuit coupled between an input at which an input signal is received and an output at which an output signal is delivered, and a refractory circuit inhibiting the integrator circuit after the delivery of the output signal. The refractory circuit is formed by a first MOS transistor having a first conduction-terminal coupled to a supply node, a second conduction-terminal coupled to a common node, and a control-terminal coupled to the output, and a second MOS transistor having a first conduction-terminal coupled to the input, a second conduction-terminal coupled to a reference node at which a reference voltage is received, and a control-terminal coupled to the common node. A resistive-capacitive circuit is coupled between the supply node and the reference node and having a tap coupled to the common node, with the inhibition duration being dependent upon a time constant of the resistive-capacitive circuit.

公开(公告)号：US20210020663A1

公开(公告)日：2021-01-21

申请号：US16926128

申请日：2020-07-10

Applicant: STMicroelectronics SA

Inventor： Philippe GALY ,  Thomas BEDECARRATS

IPC: H01L27/12

Abstract: An integrated circuit includes a MOS transistor that is located in and on a semiconductor film of a silicon-on-insulator (SOI) substrate. The SOI substrate has, below a buried insulator layer, a first back gate region and two first auxiliary regions that are located, respectively, below source and drain contact regions of the MOS transistor. The conductivity type of the two first auxiliary regions is the opposite the conductivity type of the first back gate region. The conductivity type of the two first auxiliary regions is identical to the conductivity type of the source and drain contact regions of the MOS transistor.

公开(公告)号：US20190164973A1

公开(公告)日：2019-05-30

申请号：US16199810

申请日：2018-11-26

Applicant: STMicroelectronics SA

Inventor： Hassan EL DIRANI ,  Thomas BEDECARRATS ,  Philippe GALY

IPC: H01L27/108 ,  G11C11/402 ,  G11C11/409

Abstract: A memory array includes memory cells of Z2-FET type arranged in rows and columns, wherein each memory cell includes a MOS-type selection transistor and a first region of a first conductivity type that is shared in common with a drain region of the first conductivity type of the selection transistors. The selection transistors of a same column of the memory array have a common drain region, a common source region, and a common channel region.