Invention Application
- Patent Title: ERROR TOLERANT MEMORY ARRAY AND METHOD FOR PERFORMING ERROR CORRECTION IN A MEMORY ARRAY
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Application No.: US16588916Application Date: 2019-09-30
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Publication No.: US20210073072A1Publication Date: 2021-03-11
- Inventor: John L. McCollum
- Applicant: Microchip Technology Inc.
- Applicant Address: US AZ Chandler
- Assignee: Microchip Technology Inc.
- Current Assignee: Microchip Technology Inc.
- Current Assignee Address: US AZ Chandler
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G11C16/26 ; G11C16/08 ; G11C16/10

Abstract:
A method for providing error correction for a memory array includes for each memory word stored in a data memory portion of the memory array having at least one bit error, storing in an error PROM error data identifying a memory address for the data word in the data memory portion, a bit position of each bit error, and correct bit data for each bit error, monitoring memory addresses presented to the data PROM, if a memory address presented to the data memory portion is an identified memory address, reading from the error PROM the bit position of each bit error and the correct bit data for each bit error, and substituting the correct bit data into each identified bit position of a sense amplifier reading data from the data memory portion.
Public/Granted literature
- US11068341B2 Error tolerant memory array and method for performing error correction in a memory array Public/Granted day:2021-07-20
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