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公开(公告)号：US20220262434A1
公开(公告)日：2022-08-18
申请号：US17736563
申请日：2022-05-04
Applicant: Microchip Technology Inc.
Inventor： Victor Nguyen , Fethi Dhaoui , John L. McCollum , Fengliang Xue
Abstract: A ReRAM memory array includes ReRAM memory cells and a select circuit having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.
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公开(公告)号：US20200327937A1
公开(公告)日：2020-10-15
申请号：US16405895
申请日：2019-05-07
Applicant: Microchip Technology Inc.
Inventor： Victor Nguyen , Fethi Dhaoui , John L. McCollum , Fengliang Xue
Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.
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Patent Agency Ranking
3.发明申请公开(公告)号：US20200327938A1
公开(公告)日：2020-10-15
申请号：US16405936
申请日：2019-05-07
Applicant: Microchip Technology Inc.
Inventor： Fengliang Xue , Fethi Dhaoui , Victor Nguyen , John L. McCollum
IPC: G11C13/00
Abstract: A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.
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公开(公告)号：US20210005256A1
公开(公告)日：2021-01-07
申请号：US16525546
申请日：2019-07-29
Applicant: Microchip Technology Inc.
Inventor： John L. McCollum , Fengliang Xue
IPC: G11C13/00
Abstract: A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path.
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公开(公告)号：US11068341B2
公开(公告)日：2021-07-20
申请号：US16588916
申请日：2019-09-30
Applicant: Microchip Technology Inc.
Inventor： John L. McCollum
Abstract: A method for providing error correction for a memory array includes for each memory word stored in a data memory portion of the memory array having at least one bit error, storing in an error PROM error data identifying a memory address for the data word in the data memory portion, a bit position of each bit error, and correct bit data for each bit error, monitoring memory addresses presented to the data PROM, if a memory address presented to the data memory portion is an identified memory address, reading from the error PROM the bit position of each bit error and the correct bit data for each bit error, and substituting the correct bit data into each identified bit position of a sense amplifier reading data from the data memory portion.
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公开(公告)号：US20210073072A1
公开(公告)日：2021-03-11
申请号：US16588916
申请日：2019-09-30
Applicant: Microchip Technology Inc.
Inventor： John L. McCollum
Abstract: A method for providing error correction for a memory array includes for each memory word stored in a data memory portion of the memory array having at least one bit error, storing in an error PROM error data identifying a memory address for the data word in the data memory portion, a bit position of each bit error, and correct bit data for each bit error, monitoring memory addresses presented to the data PROM, if a memory address presented to the data memory portion is an identified memory address, reading from the error PROM the bit position of each bit error and the correct bit data for each bit error, and substituting the correct bit data into each identified bit position of a sense amplifier reading data from the data memory portion.
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公开(公告)号：US10910050B2
公开(公告)日：2021-02-02
申请号：US16405895
申请日：2019-05-07
Applicant: Microchip Technology Inc.
Inventor： Victor Nguyen , Fethi Dhaoui , John L. McCollum , Fengliang Xue
Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.
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