Invention Application
- Patent Title: METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE
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Application No.: US17154241Application Date: 2021-01-21
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Publication No.: US20210142857A1Publication Date: 2021-05-13
- Inventor: Chung-Zen CHEN , Yang-Chieh LIN , Chung-Shan KUO
- Applicant: Conversant Intellectual Property Management Inc.
- Applicant Address: CA Ottawa
- Assignee: Conversant Intellectual Property Management Inc.
- Current Assignee: Conversant Intellectual Property Management Inc.
- Current Assignee Address: CA Ottawa
- Main IPC: G11C16/14
- IPC: G11C16/14 ; G11C16/16 ; G11C16/08 ; G11C16/02 ; G11C16/04

Abstract:
A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal
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