- 专利标题: NAND PARITY INFORMATION TECHNIQUES FOR SYSTEMS WITH LIMITED RAM
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申请号: US17228425申请日: 2021-04-12
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公开(公告)号: US20210303394A1公开(公告)日: 2021-09-30
- 发明人: Harish Reddy Singidi , Xiangang Luo , Jianmin Huang , Kishore Kumar Muchherla , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Sampath Ratnam
- 申请人: Micron Technology, Inc.
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 主分类号: G06F11/10
- IPC分类号: G06F11/10 ; G11C7/10 ; G11C11/419 ; G06F12/02
摘要:
Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.