Invention Application
- Patent Title: LATE GATE CUT WITH OPTIMIZED CONTACT TRENCH SIZE
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Application No.: US16832167Application Date: 2020-03-27
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Publication No.: US20210305093A1Publication Date: 2021-09-30
- Inventor: Alexander Reznicek , Balasubramanian S. Pranatharthi Haran , Praneet Adusumilli , Ruilong Xie
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/8238 ; H01L29/78 ; H01L29/66 ; H01L29/40 ; H01L29/423 ; H01L27/092

Abstract:
A semiconductor structure is provided including a gate cut region in which the contact trench size has been optimized to increase local interconnect connectivity. The semiconductor structure can include at least one gate structure located laterally adjacent to a gate cut region. At least one metal-containing contact structure is located in the gate cut region, wherein the at least one at least one metal-containing contact structure is confined by a pair of gate dielectric spacers, wherein a first gate dielectric spacer of the pair of gate dielectric spacers has a first width and is located laterally adjacent to the at least one gate structure, and a second gate dielectric spacer of the pair of gate dielectric spacers has a second width and is located laterally adjacent to the at least one metal-containing contact structure, wherein the first width is greater than the second width.
Public/Granted literature
- US11133217B1 Late gate cut with optimized contact trench size Public/Granted day:2021-09-28
Information query
IPC分类: