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    Phase change memory with conductive rings
    1.
    发明授权
    Phase change memory with conductive rings 有权

    公开(公告)号：US12219884B2

    公开(公告)日：2025-02-04

    申请号：US17449515

    申请日：2021-09-30

    Applicant: International Business Machines Corporation

    Inventor： Kangguo Cheng ,  Carl Radens ,  Juntao Li ,  Ruilong Xie ,  Praneet Adusumilli ,  Oscar van der Straten ,  Alexander Reznicek ,  Zuoguang Liu ,  Arthur Gasasira

    IPC: H10N70/20 ,  H10N70/00

    Abstract: A phase change memory, system, and method for gradually changing the conductance and resistance of the phase change memory while preventing resistance drift. The phase change memory may include a phase change material. The phase change memory may also include a bottom electrode. The phase change memory may also include a heater core proximately connected to the bottom electrode. The phase change memory may also include a set of conductive rings surrounding the heater core, where the set of conductive rings comprises one or more conductive rings, and where the set of conductive rings are proximately connected to the phase change material. The phase change memory may also include a set of spacers, where a spacer, from the set of spacers, separates a portion of a conductive ring, from the set of conductive rings, from the heater core.

    Multilayer dielectric for metal-insulator-metal capacitor
    2.
    发明授权
    Multilayer dielectric for metal-insulator-metal capacitor 有权

    公开(公告)号：US11916099B2

    公开(公告)日：2024-02-27

    申请号：US17341489

    申请日：2021-06-08

    Applicant: International Business Machines Corporation

    Inventor： Takashi Ando ,  Reinaldo Vega ,  David Wolpert ,  Cheng Chi ,  Praneet Adusumilli

    IPC: H01L29/51 ,  H01L49/02

    CPC classification number: H01L28/60 ,  H01L29/516

    Abstract: A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.

    PHASE CHANGE MEMORY WITH CONDUCTIVE RINGS
    4.
    发明申请
    PHASE CHANGE MEMORY WITH CONDUCTIVE RINGS 有权

    公开(公告)号：US20220416157A1

    公开(公告)日：2022-12-29

    申请号：US17449515

    申请日：2021-09-30

    Applicant: International Business Machines Corporation

    Inventor： Kangguo Cheng ,  Carl Radens ,  Juntao Li ,  Ruilong Xie ,  Praneet Adusumilli ,  Oscar van der Straten ,  Alexander Reznicek ,  Zuoguang Liu ,  Arthur Gasasira

    IPC: H01L45/00

    Abstract: A phase change memory, system, and method for gradually changing the conductance and resistance of the phase change memory while preventing resistance drift. The phase change memory may include a phase change material. The phase change memory may also include a bottom electrode. The phase change memory may also include a heater core proximately connected to the bottom electrode. The phase change memory may also include a set of conductive rings surrounding the heater core, where the set of conductive rings comprises one or more conductive rings, and where the set of conductive rings are proximately connected to the phase change material. The phase change memory may also include a set of spacers, where a spacer, from the set of spacers, separates a portion of a conductive ring, from the set of conductive rings, from the heater core.

    RESISTANCE DRIFT MITIGATION IN NON-VOLATILE MEMORY CELL
    6.
    发明申请
    RESISTANCE DRIFT MITIGATION IN NON-VOLATILE MEMORY CELL 有权

    公开(公告)号：US20220173312A1

    公开(公告)日：2022-06-02

    申请号：US17106286

    申请日：2020-11-30

    Applicant: International Business Machines Corporation

    Inventor： Praneet Adusumilli ,  Anirban Chandra ,  Takashi Ando ,  Cheng Chi ,  Reinaldo Vega

    IPC: H01L45/00

    Abstract: A mushroom-type Phase-Change Memory (PCM) device includes a substrate, a lower interconnect disposed in the substrate, a first dielectric layer disposed on the substrate, a bottom electrode disposed in the first dielectric layer and extending above an upper surface of the first dielectric layer, a type drift-mitigation liner encircling an upper portion of the bottom electrode extending above the upper surface of the first dielectric layer, a PCM element disposed on the liner and an upper surface of the bottom electrode, a top electrode disposed on the PCM element, and a second dielectric layer disposed on an exposed portion of the first dielectric layer and the top electrode, wherein the second dielectric layer is disposed on sidewalls of the liner, the PCM element, and the top electrode.

    LATE GATE CUT WITH OPTIMIZED CONTACT TRENCH SIZE
    9.
    发明申请
    LATE GATE CUT WITH OPTIMIZED CONTACT TRENCH SIZE 有权

    公开(公告)号：US20210305093A1

    公开(公告)日：2021-09-30

    申请号：US16832167

    申请日：2020-03-27

    Applicant: International Business Machines Corporation

    Inventor： Alexander Reznicek ,  Balasubramanian S. Pranatharthi Haran ,  Praneet Adusumilli ,  Ruilong Xie

    IPC: H01L21/768 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L27/092

    Abstract: A semiconductor structure is provided including a gate cut region in which the contact trench size has been optimized to increase local interconnect connectivity. The semiconductor structure can include at least one gate structure located laterally adjacent to a gate cut region. At least one metal-containing contact structure is located in the gate cut region, wherein the at least one at least one metal-containing contact structure is confined by a pair of gate dielectric spacers, wherein a first gate dielectric spacer of the pair of gate dielectric spacers has a first width and is located laterally adjacent to the at least one gate structure, and a second gate dielectric spacer of the pair of gate dielectric spacers has a second width and is located laterally adjacent to the at least one metal-containing contact structure, wherein the first width is greater than the second width.

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