- 专利标题: NO-ENABLE SETUP CLOCK GATER BASED ON PULSE
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申请号: US16862071申请日: 2020-04-29
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公开(公告)号: US20210344344A1公开(公告)日: 2021-11-04
- 发明人: Vivekanandan Venugopal , Shuyan Lei , Wenhao Li , Hemangi U. Gajjewar
- 申请人: Apple Inc.
- 申请人地址: US CA Cupertino
- 专利权人: Apple Inc.
- 当前专利权人: Apple Inc.
- 当前专利权人地址: US CA Cupertino
- 主分类号: H03K19/094
- IPC分类号: H03K19/094 ; G06F1/10 ; H03K17/284
摘要:
Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.
公开/授权文献
- US11258446B2 No-enable setup clock gater based on pulse 公开/授权日:2022-02-22