公开(公告)号：US11258446B2

公开(公告)日：2022-02-22

申请号：US16862071

申请日：2020-04-29

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Shuyan Lei ,  Wenhao Li ,  Hemangi U. Gajjewar

IPC: H03K3/017 ,  H03K5/04 ,  H03K7/08 ,  H03K19/094 ,  H03K17/284 ,  G06F1/10

Abstract: Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.

公开(公告)号：US20210344344A1

公开(公告)日：2021-11-04

申请号：US16862071

申请日：2020-04-29

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Shuyan Lei ,  Wenhao Li ,  Hemangi U. Gajjewar

IPC: H03K19/094 ,  G06F1/10 ,  H03K17/284

Abstract: Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.