公开(公告)号：US10453505B2

公开(公告)日：2019-10-22

申请号：US15912449

申请日：2018-03-05

申请人： Apple Inc.

发明人： Greg M. Hess ,  Hemangi U. Gajjewar

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C5/14 ,  G11C11/419

摘要： An apparatus is disclosed, including a plurality of memory cells, in which a given memory cell is coupled to a true bit line, a complement bit line, and a power supply signal. The apparatus also includes a pre-charge circuit that is configured to charge, for a first duration, the true bit line and the complement bit line to a voltage level that is less than a voltage level of the power supply signal. The pre-charge circuit is also configured to maintain, for a second duration that is longer than the first duration, the voltage level on the true bit line and the complement bit line.

公开(公告)号：US10833664B2

公开(公告)日：2020-11-10

申请号：US15676752

申请日：2017-08-14

申请人： Apple Inc.

发明人： Greg M. Hess ,  Hemangi U. Gajjewar ,  Sachmanik Cheema

IPC分类号： H03K5/159 ,  H03K19/0175 ,  H03K5/00 ,  G06F30/30

摘要： An apparatus for delaying a signal transition is disclosed. The apparatus includes a first circuit coupled to a first power supply signal and a second, different power supply signal. The first circuit may be configured to, based on a voltage level of a logic signal, sink a current from an intermediate circuit node. A value of the current may be based upon a voltage level of the second different power supply signal. The apparatus also includes a second circuit coupled to the first power supply signal. The second circuit may be configured to generate an output signal based upon a voltage level of the intermediate circuit node. An amount of time between a transition of the logic signal and a corresponding transition of the output signal may be based on an amount of the current.

公开(公告)号：US11258446B2

公开(公告)日：2022-02-22

申请号：US16862071

申请日：2020-04-29

申请人： Apple Inc.

发明人： Vivekanandan Venugopal ,  Shuyan Lei ,  Wenhao Li ,  Hemangi U. Gajjewar

IPC分类号： H03K3/017 ,  H03K5/04 ,  H03K7/08 ,  H03K19/094 ,  H03K17/284 ,  G06F1/10

摘要： Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.

公开(公告)号：US20190052254A1

公开(公告)日：2019-02-14

申请号：US15676752

申请日：2017-08-14

申请人： Apple Inc.

发明人： Greg M. Hess ,  Hemangi U. Gajjewar ,  Sachmanik Cheema

IPC分类号： H03K5/159 ,  H03K19/0175

摘要： An apparatus for delaying a signal transition is disclosed. The apparatus includes a first circuit coupled to a first power supply signal and a second, different power supply signal. The first circuit may be configured to, based on a voltage level of a logic signal, sink a current from an intermediate circuit node. A value of the current may be based upon a voltage level of the second different power supply signal. The apparatus also includes a second circuit coupled to the first power supply signal. The second circuit may be configured to generate an output signal based upon a voltage level of the intermediate circuit node. An amount of time between a transition of the logic signal and a corresponding transition of the output signal may be based on an amount of the current.

公开(公告)号：US20210344344A1

公开(公告)日：2021-11-04

申请号：US16862071

申请日：2020-04-29

申请人： Apple Inc.

发明人： Vivekanandan Venugopal ,  Shuyan Lei ,  Wenhao Li ,  Hemangi U. Gajjewar

IPC分类号： H03K19/094 ,  G06F1/10 ,  H03K17/284

摘要： Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.

公开(公告)号：US10908663B2

公开(公告)日：2021-02-02

申请号：US16433801

申请日：2019-06-06

申请人： Apple Inc.

发明人： Victor Zyuban ,  Greg M. Hess ,  Hemangi U. Gajjewar

IPC分类号： G06F1/26 ,  H02J1/08 ,  H03K17/22 ,  H03K19/00 ,  H03K19/173 ,  H03K17/693

摘要： A power switch multiplexer with configurable overlap is disclosed. An integrated circuit (IC) includes a first functional circuit block coupled to receive a supply voltage from a first supply voltage node. The IC further includes an input circuit and an output circuit. Responsive to receiving an input signal, the input circuit asserts an activation signal to cause one of a second supply voltage node and a third supply voltage node to be electrically coupled to the first supply voltage node. Subsequently the input circuit asserts a deactivation signal to cause the other one of the second and third supply voltage nodes to be electrically decoupled from the first supply voltage node. The output circuit is coupled to receive the activation signal and the deactivation signal, and configured to assert a first output signal subsequent to receiving the activation signal.

公开(公告)号：US20190272859A1

公开(公告)日：2019-09-05

申请号：US15912449

申请日：2018-03-05

申请人： Apple Inc.

发明人： Greg M. Hess ,  Hemangi U. Gajjewar

IPC分类号： G11C7/12 ,  G11C11/419 ,  G11C5/14

摘要： An apparatus is disclosed, including a plurality of memory cells, in which a given memory cell is coupled to a true bit line, a complement bit line, and a power supply signal. The apparatus also includes a pre-charge circuit that is configured to charge, for a first duration, the true bit line and the complement bit line to a voltage level that is less than a voltage level of the power supply signal. The pre-charge circuit is also configured to maintain, for a second duration that is longer than the first duration, the voltage level on the true bit line and the complement bit line.