Invention Application
- Patent Title: Graphene-Assisted Low-Resistance Interconnect Structures and Methods of Formation Thereof
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Application No.: US17391216Application Date: 2021-08-02
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Publication No.: US20220020694A1Publication Date: 2022-01-20
- Inventor: Shin-Yi Yang , Yu-Chen Chan , Ming-Han Lee , Hai-Ching Chen , Shau-Lin Shue
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L23/532
- IPC: H01L23/532 ; H01L21/768 ; H01L23/522
Abstract:
A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.
Public/Granted literature
- US11710700B2 Graphene-assisted low-resistance interconnect structures and methods of formation thereof Public/Granted day:2023-07-25
Information query
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