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    GRAPHENE-ASSISTED LOW-RESISTANCE INTERCONNECT STRUCTURES AND METHODS OF FORMATION THEREOF
    2.
    发明申请
    GRAPHENE-ASSISTED LOW-RESISTANCE INTERCONNECT STRUCTURES AND METHODS OF FORMATION THEREOF 有权

    公开(公告)号：US20240379559A1

    公开(公告)日：2024-11-14

    申请号：US18780834

    申请日：2024-07-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shin-Yi Yang ,  Yu-Chen Chan ,  Ming-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

    IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first conductive feature and a second conductive feature disposed in an interlayer dielectric (ILD) layer. The semiconductor structure includes a first graphene layer disposed over the first conductive feature and a second graphene layer disposed over a portion of the second conductive feature. An etch-stop layer (ESL) is horizontally interposed between the first graphene layer and the second graphene layer. A side surface of the first or the second graphene layer directly contacts a side surface of the ESL. A third conductive feature is electrically coupled to the second conductive feature. The third conductive feature is separated from the first graphene layer by a portion of the ESL, and the third conductive feature also directly contacts a top surface of the ESL.

    TWO 2D CAPPING LAYERS ON INTERCONNECT CONDUCTIVE STRUCTURE TO INCREASE INTERCONNECT STRUCTURE RELIABILITY
    3.
    发明申请
    TWO 2D CAPPING LAYERS ON INTERCONNECT CONDUCTIVE STRUCTURE TO INCREASE INTERCONNECT STRUCTURE RELIABILITY 有权

    公开(公告)号：US20220157710A1

    公开(公告)日：2022-05-19

    申请号：US17097406

    申请日：2020-11-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shu-Wei Li ,  Yu-Chen Chan ,  Shin-Yi Yang ,  Ming-Han Lee

    IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. A first interconnect conductive structure extends through the first interconnect dielectric layer. A first capping layer is arranged over the first interconnect conductive structure, and a second capping layer is arranged over the first capping layer. The first capping layer includes a first two-dimensional material that is different than a second two-dimensional material of the second capping layer. An etch stop layer is arranged over the first interconnect dielectric layer and the second capping layer. The integrated chip further includes a second interconnect dielectric layer arranged over the etch stop layer and a second interconnect conductive structure extending through the second interconnect dielectric layer and the etch stop layer to contact the first interconnect conductive structure.

    Method of forming interconnection structure
    4.
    发明授权
    Method of forming interconnection structure 有权

    公开(公告)号：US11011467B2

    公开(公告)日：2021-05-18

    申请号：US16988636

    申请日：2020-08-08

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yu-Chen Chan ,  Shin-Yi Yang ,  Ming-Han Lee

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/285

    Abstract: A method includes depositing an etch stop layer over a non-insulator structure and a dielectric layer over the etch stop layer; etching the dielectric layer to form a first hole in the dielectric layer; deepening the first hole into the etch stop layer such that the non-insulator structure is exposed at a bottom of the deepened hole; after the non-insulator structure is exposed, performing a cleaning operation to remove etch byproducts from the deepened first hole, wherein the cleaning operation results in lateral recesses laterally extending from a bottom portion of the deepened first hole into the etch stop layer; depositing a first diffusion barrier layer into the deepened first hole until the lateral recesses are overfilled; depositing a second diffusion barrier layer over the first diffusion barrier layer; and depositing one or more conductive layers over the second diffusion barrier layer.

    Two 2D capping layers on interconnect conductive structure to increase interconnect structure reliability
    6.
    发明授权
    Two 2D capping layers on interconnect conductive structure to increase interconnect structure reliability 有权

    公开(公告)号：US11532549B2

    公开(公告)日：2022-12-20

    申请号：US17097406

    申请日：2020-11-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shu-Wei Li ,  Yu-Chen Chan ,  Shin-Yi Yang ,  Ming-Han Lee

    IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. A first interconnect conductive structure extends through the first interconnect dielectric layer. A first capping layer is arranged over the first interconnect conductive structure, and a second capping layer is arranged over the first capping layer. The first capping layer includes a first two-dimensional material that is different than a second two-dimensional material of the second capping layer. An etch stop layer is arranged over the first interconnect dielectric layer and the second capping layer. The integrated chip further includes a second interconnect dielectric layer arranged over the etch stop layer and a second interconnect conductive structure extending through the second interconnect dielectric layer and the etch stop layer to contact the first interconnect conductive structure.

    Protection liner on interconnect wire to enlarge processing window for overlying interconnect via
    7.
    发明授权
    Protection liner on interconnect wire to enlarge processing window for overlying interconnect via 有权

    公开(公告)号：US11309241B2

    公开(公告)日：2022-04-19

    申请号：US16908942

    申请日：2020-06-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shin-Yi Yang ,  Hsin-Yen Huang ,  Ming-Han Lee ,  Shau-Lin Shue ,  Yu-Chen Chan ,  Meng-Pei Lu

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.

    Interconnection structure and method for forming the same
    10.
    发明授权
    Interconnection structure and method for forming the same 有权

    公开(公告)号：US10741493B2

    公开(公告)日：2020-08-11

    申请号：US16200076

    申请日：2018-11-26

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yu-Chen Chan ,  Shin-Yi Yang ,  Ming-Han Lee

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/285

    Abstract: A structure includes a non-insulator structure, an etch stop layer, a dielectric layer, a conductive feature, and a first diffusion barrier layer. The etch stop layer is over the non-insulator structure. The dielectric layer is over the etch stop layer. The conductive feature is in the dielectric layer. The first diffusion barrier layer wraps around the conductive feature, the first diffusion barrier layer has a base portion between the non-insulator structure and the conductive feature, and the first diffusion barrier layer has a lateral extension from the base portion of the first diffusion barrier layer.

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