Invention Application
- Patent Title: Scalable Cache Coherency Protocol
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Application No.: US17315725Application Date: 2021-05-10
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Publication No.: US20220083472A1Publication Date: 2022-03-17
- Inventor: James Vash , Gaurav Garg , Brian P. Lilly , Ramesh B. Gunna , Steven R. Hutsell , Lital Levy-Rubin , Per H. Hammarlund
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Main IPC: G06F12/0815
- IPC: G06F12/0815

Abstract:
A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.
Public/Granted literature
- US11544193B2 Scalable cache coherency protocol Public/Granted day:2023-01-03
Information query
IPC分类: