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    Memory error tracking and logging
    1.
    发明授权
    Memory error tracking and logging 有权

    公开(公告)号：US12253913B2

    公开(公告)日：2025-03-18

    申请号：US18438802

    申请日：2024-02-12

    Applicant: Apple Inc.

    Inventor： Farid Nemati ,  Steven R. Hutsell ,  Derek R. Kumar ,  Bernard J. Semeria ,  James Vash ,  Era K. Nangia ,  Gregory S. Mathews

    IPC: G06F11/10 ,  G06F11/07

    Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.

    Multiple Independent On-chip Interconnect
    5.
    发明申请
    Multiple Independent On-chip Interconnect 有权

    公开(公告)号：US20220334997A1

    公开(公告)日：2022-10-20

    申请号：US17337805

    申请日：2021-06-03

    Applicant: Apple Inc.

    Inventor： Sergio Kolor ,  Sergio V. Tota ,  Tzach Zemer ,  Sagi Lahav ,  Jonathan M. Redshaw ,  Per H. Hammarlund ,  Eran Tamari ,  James Vash ,  Gaurav Garg

    IPC: G06F13/40 ,  G06F15/173

    Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

    Scalable Cache Coherency Protocol
    6.
    发明申请
    Scalable Cache Coherency Protocol 有权

    公开(公告)号：US20220083472A1

    公开(公告)日：2022-03-17

    申请号：US17315725

    申请日：2021-05-10

    Applicant: Apple Inc.

    Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund

    IPC: G06F12/0815

    Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

    DSB Operation with Excluded Region
    7.
    发明申请
    DSB Operation with Excluded Region 有权

    公开(公告)号：US20220083338A1

    公开(公告)日：2022-03-17

    申请号：US17469504

    申请日：2021-09-08

    Applicant: Apple Inc.

    Inventor： Jeff Gonion ,  John H. Kelm ,  James Vash ,  Pradeep Kanapathipillai ,  Mridul Agarwal ,  Gideon N. Levinsky ,  Richard F. Russo ,  Christopher M. Tsay

    IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/02

    Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

    Remote Cache Invalidation
    8.
    发明申请
    Remote Cache Invalidation 有权

    公开(公告)号：US20250103492A1

    公开(公告)日：2025-03-27

    申请号：US18582305

    申请日：2024-02-20

    Applicant: Apple Inc.

    Inventor： Brett S. Feero ,  Dennis R. Bradford ,  Gaurav Garg ,  Jeff Gonion ,  Bernard J. Semeria ,  James Vash ,  Richard F. Russo

    IPC: G06F12/0808 ,  G06F12/0882 ,  G06F12/1045

    Abstract: Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.

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