公开(公告)号：US12189565B2

公开(公告)日：2025-01-07

申请号：US18306087

申请日：2023-04-24

Applicant: Apple Inc.

Inventor： Igor Tolchinsky ,  Charles J. Fleckenstein ,  Sagi Lahav ,  Lital Levy-Rubin

IPC: G06F13/40 ,  G06F13/42

Abstract: In an embodiment, an SOC includes a global communication fabric that includes multiple independent networks having different communication and coherency protocols, and a plurality of input-output (I/O) clusters that includes different sets of local functional circuits. A given I/O cluster may be coupled to one or more of the independent networks and may include a particular set of local functional circuits, a local fabric coupled to the particular set of local functional circuits, and an interface circuit coupled to the local fabric and configured to bridge transactions between the particular set of local functional circuits and the global communication fabric. The interface circuit may include a programmable hardware transaction generator circuit configured to generate a set of test transactions that simulate interactions between the particular set of local functional circuits and a particular one of the one or more independent networks.

公开(公告)号：US12067275B1

公开(公告)日：2024-08-20

申请号：US17810275

申请日：2022-06-30

Applicant: Apple Inc.

Inventor： Samer Nassar ,  Sagi Lahav ,  Lital Levy-Rubin ,  Roey Grinvald

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0676 ,  G06F3/0679

Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a memory bank and be coupled to a set of devices. The I/O agent circuit may assign a device of the set of devices to a subdomain of a plurality of subdomains implemented for the memory bank. The I/O agent circuit may store, in that memory bank, a set of transactions of the device in association with the subdomain assigned to the device. The I/O agent circuit may execute the set of transactions such that transactions stored in the memory bank in association with other ones of the plurality of subdomains than the subdomain assigned to the device do not block execution of the set of transactions.

公开(公告)号：US20220083472A1

公开(公告)日：2022-03-17

申请号：US17315725

申请日：2021-05-10

Applicant: Apple Inc.

Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund

IPC: G06F12/0815

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

公开(公告)号：US11822411B2

公开(公告)日：2023-11-21

申请号：US17313837

申请日：2021-05-06

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Karl Daniel Wulcan ,  Lital Levy-Rubin ,  Tal Kuzi

IPC: G06F1/3206 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F1/3206 ,  G06F11/3003 ,  G06F11/3062 ,  G06F11/3495

Abstract: Systems, apparatuses, and methods for implementing telemetry push aggregation techniques are described. A computing system includes one or more input/output (I/O) agents interposed between functional units and a communication fabric. A given I/O agent receives a set of aggregation rules from a power management unit. The I/O agent monitors traffic from the functional units, and the I/O agent generates telemetry data from the traffic data based on the set of aggregation rules. The telemetry data is used by the power management unit to make adjustments to one or more power settings.

公开(公告)号：US11803471B2

公开(公告)日：2023-10-31

申请号：US17821312

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Lior Zimet ,  Sergio Kolor ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Tal Kuzi ,  Jeffry E. Gonion ,  Charles E. Tucker ,  Lital Levy-Rubin ,  Dany Davidov ,  Steven Fishwick ,  Nir Leshem ,  Mark Pilip ,  Gerard R. Williams, III ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F13/28 ,  G06F13/16 ,  G06F13/40 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F12/128 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4068 ,  G06F15/17368 ,  G06F15/7807 ,  G06F2212/305 ,  G06F2212/657

Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

公开(公告)号：US11550716B2

公开(公告)日：2023-01-10

申请号：US17648071

申请日：2022-01-14

Applicant: Apple Inc.

Inventor： Gaurav Garg ,  Sagi Lahav ,  Lital Levy-Rubin ,  Gerard Williams, III ,  Samer Nassar ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Jeff Gonion ,  James Vash

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/0891 ,  G06F9/46 ,  G06F13/16 ,  G06F12/0831

Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

公开(公告)号：US20250097166A1

公开(公告)日：2025-03-20

申请号：US18433184

申请日：2024-02-05

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Dan Darel ,  Lior Zimet ,  Lital Levy-Rubin ,  Opher Kahn ,  Roi Uziel ,  Sagi Lahav ,  Shawn M. Fukami ,  Tzach Zemer

IPC: H04L49/25 ,  H04L49/00

Abstract: An apparatus includes first agents configured to transfer transactions using an ordered protocol, as well as second agents configured to transfer transactions using a protocol with no enforced ordering. The apparatus may also include input/output (I/O) interfaces coupled to respective ones of the first agents and configured to enforce the ordered protocol. The apparatus may further include a communication network including a plurality of network switches. A particular one of the network switches may be coupled to at least one other network switch of the plurality. The apparatus may also include a network interface coupled to the second agents, to the I/O interfaces, and to the particular network switch. This network interface may be configured to transfer data transactions between the second agents and the particular network switch, and to transfer data transactions between the I/O interfaces and the particular network switch.

公开(公告)号：US20240160267A1

公开(公告)日：2024-05-16

申请号：US18510525

申请日：2023-11-15

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Karl Daniel Wulcan ,  Lital Levy-Rubin ,  Tal Kuzi

IPC: G06F1/3206 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F1/3206 ,  G06F11/3003 ,  G06F11/3062 ,  G06F11/3495

Abstract: Systems, apparatuses, and methods for implementing telemetry push aggregation techniques are described. A computing system includes one or more input/output (I/O) agents interposed between functional units and a communication fabric. A given I/O agent receives a set of aggregation rules from a power management unit. The I/O agent monitors traffic from the functional units, and the I/O agent generates telemetry data from the traffic data based on the set of aggregation rules. The telemetry data is used by the power management unit to make adjustments to one or more power settings.

公开(公告)号：US11941428B2

公开(公告)日：2024-03-26

申请号：US17657506

申请日：2022-03-31

Applicant: Apple Inc.

Inventor： Sagi Lahav ,  Lital Levy-Rubin ,  Gaurav Garg ,  Gerard R. Williams, III ,  Samer Nassar ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Jeff Gonion

IPC: G06F9/46 ,  G06F13/16 ,  H04L49/00

CPC classification number: G06F9/466 ,  G06F13/1668

Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.

公开(公告)号：US20230334003A1

公开(公告)日：2023-10-19

申请号：US18306087

申请日：2023-04-24

Applicant: Apple Inc.

Inventor： Igor Tolchinsky ,  Charles J. Fleckenstein ,  Sagi Lahav ,  Lital Levy-Rubin

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4282 ,  G06F13/4027 ,  G06F2213/0038 ,  G06F2213/0042

Abstract: In an embodiment, an SOC includes a global communication fabric that includes multiple independent networks having different communication and coherency protocols, and a plurality of input-output (I/O) clusters that includes different sets of local functional circuits. A given I/O cluster may be coupled to one or more of the independent networks and may include a particular set of local functional circuits, a local fabric coupled to the particular set of local functional circuits, and an interface circuit coupled to the local fabric and configured to bridge transactions between the particular set of local functional circuits and the global communication fabric. The interface circuit may include a programmable hardware transaction generator circuit configured to generate a set of test transactions that simulate interactions between the particular set of local functional circuits and a particular one of the one or more independent networks.