Invention Application
- Patent Title: TECHNIQUES FOR DIE TILING
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Application No.: US17556660Application Date: 2021-12-20
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Publication No.: US20220115367A1Publication Date: 2022-04-14
- Inventor: Srinivas PIETAMBARAM , Gang DUAN , Deepak KULKARNI
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L23/48 ; H01L23/538 ; H01L23/29 ; H01L21/683 ; H01L23/31

Abstract:
Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.
Information query
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